RISC-V Summit

RISC-V Summit

October 22-23, 2024
Santa Clara, CA
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8:00am PDT

Registration & Badge Pick-up Main Lobby (Level 1)

9:00am PDT

Applications & Tools Horizontal Committee Meeting Grand Ballroom H (Level 1) Member Day Session: Realizing RISC-V Certification, and What it Means for your Verification - Adnan Hamid, Breker Verification Systems Theater (Level 2) RISC-V 101 Grand Ballroom G (Level 1)

9:30am PDT

Member Day Session: Exploring the Programming Model of the RISC-V IOPMP - Paul Ku, Andes Technology Grand Ballroom H (Level 1) Member Day Session: RISC-V for HPC: Where We Currently are and Where We Need to Go - Nick Brown, University of Edinburgh Theater (Level 2) Automotive Market Development Meeting 206 (Level 2)

10:00am PDT

Member Day Session: CHERI 101 and Standardization Session - Tariq Kurd, Codasip Grand Ballroom H (Level 1) Member Day Session: Improving Performance Analysis on RISC-V - Beeman Strong & Atish Patra, Rivos, Inc Theater (Level 2)

10:30am PDT

11:00am PDT

Member Day Session: Verifying a CPU with Sail - Tim Hutt, Codasip Grand Ballroom H (Level 1) Security Horizontal Committee Update - Andrew Dellow, Qualcomm & Ravi Sahita, Rivos Inc. Theater (Level 2) AI Market Development Meeting 206 (Level 2)

11:30am PDT

Member Day Session: The Need for a Packed-SIMD Extension - Rich Fuhler, Andes Technology Grand Ballroom H (Level 1) Security Model Update - Nicholas Wood, Imagination Technologies Theater (Level 2) Hackathon Grand Ballroom G (Level 1)

12:00pm PDT

Member Day Session: Sailing Toward a Single Source of Truth - Paul Clarke, Ventana Micro Systems & Derek Hower, Qualcomm Grand Ballroom H (Level 1) SOC Infrastructure Horizontal Committee Update - Ved Shanbhogue, Rivos Inc. Theater (Level 2)

12:30pm PDT

Lunch (Attendees on Own)

1:30pm PDT

Unprivileged ISA Committee Update - Earl Kilian, Aril Inc. Theater (Level 2) Marketing & Events Committee Meeting Grand Ballroom H (Level 1)

2:00pm PDT

Restarting the Automotive SIG - Andrea Gallo, RISC-V Theater (Level 2)

2:30pm PDT

Member Day Session: Update on Unified Discovery - Siqi Zhao, Alibaba Inc. Grand Ballroom H (Level 1) Profiles Special Interest Group Update - David Weaver, Akeana & James Ball, Qualcomm Theater (Level 2)

3:00pm PDT

Member Day Session: Why Do We Need Yocto Project on RISC-V - Challenges and Best Practices - Khem Raj, Comcast Grand Ballroom H (Level 1) Privileged Software Horizontal Committee Annual Update - Anup Patel, Ventana Micro Systems Theater (Level 2)

3:30pm PDT

Member Day Session: A Simple Plan: An API and ABI for Managing Multiple Distinct Sets of Custom Extensions - Guy Lemieux, University of British Columbia Grand Ballroom H (Level 1) Member Day Session: Enabling New Security Frontiers: Deep-dive into Implementing Confidential Computing on RISC-V - Ravi Sahita & Atish Patra, Rivos Theater (Level 2)

4:00pm PDT

Member Day Session: High Assurance Cryptography ISE - G. Richard Newell, Microchip Technology Inc. Grand Ballroom H (Level 1) Technical Steering Committee Meeting Theater (Level 2)

4:30pm PDT

5:00pm PDT

Member Day Keynotes Theater (Level 2)

8:00am PDT

Registration & Badge Pick-up Main Lobby (Level 1)

9:00am PDT

Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International Mission City Ballroom B2 - B5 (Level 1)

9:20am PDT

Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy Mission City Ballroom B2 - B5 (Level 1)

9:40am PDT

Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA Mission City Ballroom B2 - B5 (Level 1)

10:00am PDT

Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology Mission City Ballroom B2 - B5 (Level 1)

10:15am PDT

Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys Mission City Ballroom B2 - B5 (Level 1)

10:30am PDT

Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology Mission City Ballroom B2 - B5 (Level 1)

10:45am PDT

Coffee Break Exhibit Hall A Expo Hall Exhibit Hall A

10:50am PDT

Demo: XuanTie RISC-V Hardware and Software Full-stack Technology - James Shi, Alibaba DAMO Academy Expo Hall - Exhibit Hall A - Demo Theater

11:15am PDT

Demo: Enabling Automotive Safety with Andes RISC-V IP - Marc Evans, Andes Technology Expo Hall - Exhibit Hall A - Demo Theater

11:30am PDT

Say Goodbye to Fear, Uncertainty, and Doubt: Innovate with Codasip Studio Fusion - Keith Graham, Codasip Grand Ballroom G (Level 1) RISC-V Needs More Secure “Wheels”! A Perspective for/from Automotive Industry - Thomas Roecker, Infineon Technologies & Sandro Pinto, OSYX Technologies Grand Ballroom H (Level 1) Sail RISC-V: Status and Future Challenges - Alasdair Armstrong, University of Cambridge Theater (Level 2)

11:50am PDT

Exploring Real-Time Operating System Execution Strategies on Virtual Machines in RISC-V Architecture - Ryosuke Yamamoto, Mitsubishi Electric Corporation Grand Ballroom H (Level 1) Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP Theater (Level 2) The Benefits of Building New AI Accelerators with RISC-V - Cliff Young & Martin Maas, Google DeepMind Grand Ballroom G (Level 1)

12:10pm PDT

Automotive Solution Empowered by RISC-V Based Security and Functional Safety Module - Jianying Peng, Nuclei System Technology Grand Ballroom H (Level 1) Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Technology Co., Ltd. Theater (Level 2)

12:30pm PDT

Lunch (Provided for Attendees) Exhibit Hall B (Level 1)

12:45pm PDT

Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks - Carl Shaw, Codasip Expo Hall - Exhibit Hall A - Demo Theater

12:55pm PDT

Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine - Rejeesh Shaji Babu, Ashling Expo Hall - Exhibit Hall A - Demo Theater

1:05pm PDT

Demo: More Than Point Tools: RISC-V Solutions - Larry Lapides, Synopsys Expo Hall - Exhibit Hall A - Demo Theater

1:55pm PDT

Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here - Jin Kim, Esperanto Technologies Grand Ballroom G (Level 1) CPU Security in the Context of RISC-V - Sylvain Guilley, Secure-IC Grand Ballroom H (Level 1) Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc. Theater (Level 2)

2:15pm PDT

Building Tool Chains for RISC-V AI Accelerators - Jeremy Bennett, Embecosm Grand Ballroom G (Level 1) An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications - Jamie Kim, Samsung Electronics Grand Ballroom H (Level 1) RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS Theater (Level 2)

2:35pm PDT

LLM Inference on RISC-V Embedded CPUs - Yueh-Feng Lee, Andes Technology Grand Ballroom G (Level 1) Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android - Lev Rumyantsev & Jeremiah Griffin, Google Grand Ballroom H (Level 1)

2:55pm PDT

The Future of Mission Critical Edge Compute Is RISC-V - David Levy, Microchip Grand Ballroom H (Level 1) Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys Theater (Level 2) Bridging the Gap: Compiling and Optimizing Triton Kernels Onto RISC-V Targets Based on MLIR - Aries Wu, Terapines Technology Co., Ltd. Grand Ballroom G (Level 1)

3:15pm PDT

Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension - Markku-Juhani O. Saarinen, Tampere University Grand Ballroom H (Level 1) Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm Theater (Level 2)

3:35pm PDT

HPC & Data Center Poster Sessions Expo Hall - Exhibit Hall A (Level 1) ISA & Design Tools Poster Sessions Expo Hall - Exhibit Hall A (Level 1) Security Poster Sessions Expo Hall - Exhibit Hall A (Level 1) Coffee Break Exhibit Hall A

3:40pm PDT

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics Expo Hall - Exhibit Hall A - Demo Theater

3:50pm PDT

Demo: Super-optimized Ubuntu and Open Source on RISC-V - Gordan Markuš, Canonical Expo Hall - Exhibit Hall A - Demo Theater

4:00pm PDT

Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V - Kelvin Low, Samsung Foundry Expo Hall - Exhibit Hall A - Demo Theater

4:15pm PDT

Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework Mission City Ballroom B2 - B5 (Level 1)

4:30pm PDT

Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley Mission City Ballroom B2 - B5 (Level 1)

4:50pm PDT

Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted... Mission City Ballroom B2 - B5 (Level 1)

5:30pm PDT

Attendee Reception and Booth Crawl Sponsored by Ventana Exhibit Hall A

8:00am PDT

Collaboration Breakfast - Sponsored by Google Grand Ballroom G (Level 1)

8:30am PDT

Registration & Badge Pick-up Main Lobby (Level 1)

9:00am PDT

Keynote: RISC-V State of the Union - Krste Asanović, Chief Architect, RISC-V International Mission City Ballroom B2 - B5 (Level 1)

9:20am PDT

Keynote: RISC-V Security - Current Initiatives and Future Trends - Helena Handschuh, Technical Board Advisor Mission City Ballroom B2 - B5 (Level 1)

9:38am PDT

Keynote: Launchpad Mission City Ballroom B2 - B5 (Level 1)

9:55am PDT

Keynote Panel: The Future of AI and Security - Andrew Dellow, Qualcomm; Kris Murphy, NVIDIA; Pete Bernard, tinyML Foundation; Pete Warden, Useful Sensors Inc; Andrea Gallo, RISC-V International Mission City Ballroom B2 - B5 (Level 1)

10:30am PDT

Keynote: Mobilizing the Open Source Software Ecosystem for RISC-V - Barna Ibrahim, Vice Chair of RISE Governing Board & Principal, Business Development at Rivos Inc. Mission City Ballroom B2 - B5 (Level 1)

10:45am PDT

Coffee Break Exhibit Hall A Expo Hall Exhibit Hall A

10:50am PDT

Demo: Introduction to Microchip's PIC64 Product Family and Demonstration of Video Pipeline on PIC64GX - David Levy & Dr. Battu Prakash Reddy, Microchip Expo Hall - Exhibit Hall A - Demo Theater

11:10am PDT

Demo: Andes ACE: Enabling Custom RISCV Instructions Safely - Darren Jones, Andes Technology Expo Hall - Exhibit Hall A - Demo Theater

11:30am PDT

RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos Grand Ballroom H (Level 1) Software Engineers Are Tomorrow's Processor Engineers - Keith Graham, Codasip Theater (Level 2) SiFive Event Trace: The First Zero-Overhead Performance Tool for RISC-V Processors - Carsten Gosvig, SiFive Grand Ballroom G (Level 1)

11:50am PDT

RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc. Grand Ballroom H (Level 1) RISC-V LLVM State of the Union - Alex Bradbury, Igalia Grand Ballroom G (Level 1) RISC-V Control-Flow Integrity (CFI) - Ved Shanbhogue, Rivos & George Christou, Technical University of Crete Theater (Level 2)

12:10pm PDT

Ratified N-Trace Specifications - an Overview - Robert Chyla, MIPS & Jay Gamoneda, NXP Grand Ballroom H (Level 1) Exploration of Productization of Android on RISC-V - Han Mao, Alibaba Damo Academy Grand Ballroom G (Level 1)

12:30pm PDT

Lunch (Provided for Attendees) Exhibit Hall B (Level 1)

12:45pm PDT

Demo: Accelerate RISC-V Development with Tessent UltraSight-V - Francisca Tan, Siemens EDA Expo Hall - Exhibit Hall A - Demo Theater

12:55pm PDT

Demo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips - Dennis Griffith, Lauterbach Expo Hall - Exhibit Hall A - Demo Theater

1:55pm PDT

RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built - David Chen, Stream Computing Grand Ballroom H (Level 1) Understanding the Unformated Trace & Diagnostic Data Packet Encapsulation for RISC-V Specification - Iain Robertson, Siemens EDA Theater (Level 2) GPU Program Support on RISC-V GPU - Hyesoon Kim, Georgia Tech Grand Ballroom G (Level 1)

2:00pm PDT

Hackathon Presentations Expo Hall - Exhibit Hall A - Demo Theater Career Day Expo Hall - Exhibit Hall A (Level 1)

2:15pm PDT

RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems Grand Ballroom H (Level 1) Hardening Linux and FreeBSD on RISC-V with CHERI - Carl Shaw, Codasip Theater (Level 2) Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs - Jon Taylor, Synopsys Grand Ballroom G (Level 1)

2:35pm PDT

Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers Grand Ballroom H (Level 1) Making the Case for a Keccak Instruction - Markku-Juhani O. Saarinen, Tampere University Theater (Level 2) Porting SLEEF to RISC-V - Ludovic Henry, Rivos & Eric Love, SiFive Grand Ballroom G (Level 1)

2:55pm PDT

Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive - Vasanth Waran, MIPS Grand Ballroom H (Level 1) Aggregation Optimization for SIMD Everywhere from ARM Neon to RISC-V Vector and Crypto Extensions - Jenq-Kuen Lee & Hung-Ming Lai, National Tsing-Hua University, Taiwan Grand Ballroom G (Level 1)

3:15pm PDT

AI/ML Poster Sessions Expo Hall - Exhibit Hall A (Level 1) Automotive, Embedded & Mobile Poster Sessions Expo Hall - Exhibit Hall A (Level 1) Coffee Break Exhibit Hall A

3:20pm PDT

Akeana : Breaking Performance Barriers - Graham Wilson, Akeana Expo Hall - Exhibit Hall A - Demo Theater

3:30pm PDT

RISC-V Opportunities in Brazil - J. E.Bertuzzo, Eldorado Institute Expo Hall - Exhibit Hall A - Demo Theater

3:55pm PDT

Keynote Panel: The Future of High Performance Computing is RISC-V - Luisa Gonzales, Lawrence Berkeley National Laboratory; Nick Brown, EPCC at the University of Edinburgh; Wei-Han Lien, Tenstorrent Inc. Mission City Ballroom B2 - B5 (Level 1)

4:40pm PDT

Keynote: Community Awards Mission City Ballroom B2 - B5 (Level 1)