Name: Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International
Start: 2024-10-22T09:00:00-0700
End: 2024-10-22T09:20:00-0700

October 22-23, 2024
Santa Clara, CA
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Tuesday October 22, 2024 9:00am - 9:20am PDT

Mission City Ballroom B2 - B5 (Level 1)

Over the last decade, the industry standard RISC-V Instruction Set Architecture (ISA) has profoundly changed the computing industry with billions of cores shipped and a growing ecosystem of successful businesses all betting their future on RISC-V, but this is only just the beginning. In this session, Calista Redmond will discuss three ways that RISC-V is disrupting and defining the processor industry in the next decade. The ability to customize and extend RISC-V microprocessor designs will usher in an era of workload-defined silicon, where hardware / software co-design enables faster, more efficient compute, optimized for each application. This will power the deployment of AI in mainstream applications, where the flexibility to customize will accelerate innovation and adoption of AI worldwide. This new era of computing will enable developers, industries, and countries to solve local problems, together with access to a global ecosystem and market. Come and discover the future of computing!

Speakers

Calista Redmond

CEO, RISC-V International, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Tuesday October 22, 2024 9:00am - 9:20am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

RISC-V Summit

Calista Redmond

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