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RISC-V Summit has ended
October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 12:55pm - 1:05pm PDT
RISC-V cores can be found in more and more chips - as the main CPU(s) or as a companion core together with other CPU architectures. They can be implemented in subarchitectures like RISC-V RV32/RV64, AndesCore™ V5 or SiFive® Core IP. While the complexity of SoCs grows with the number of cores and the number of different core (sub)architectures, the challenges for embedded developers grow even more with operating systems, hypervisors, and other software running on multiple cores.

In this presentation, Lauterbach, market leader for development tools and strategic member of the RISC-V foundation, show how developers can overcome these challenges with the right tools and debug strategies. They explain how to debug cores from RISC-V and other architectures simultaneously via one debug interface and one debug probe to gain insight into the entire embedded system. The presentation covers real-time on- and off-chip tracing for all major RISC-V trace systems as well as the utilization of standardized RISC-V debug and trace interfaces.

Through this presentation the attendee learns that multicore debugging with RISC-V cores is not rocket science and that there are efficient methods to master even complex chips with complex software configurations.
Speakers
avatar for Dennis Griffith

Dennis Griffith

Senior Field Applications Engineer, Lauterbach
Dennis Griffith is a Senior Field Applications Engineer at Lauterbach specializing in debugging software, hardware, and validating debugger access for complex System-on-Chip (SoC) designs. He holds a BSEE from the University of Portland and has over 20 years of experience. Dennis's... Read More →
Wednesday October 23, 2024 12:55pm - 1:05pm PDT
Expo Hall - Exhibit Hall A - Demo Theater
  Demo Theater
  • Session Slides Attached Yes
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