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October 22-23, 2024
Santa Clara, CA
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RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems
Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)
The recently ratified RERI specification provides a open and standardized register interface specification for error reporting for RISC-V based designs targeting segments from HPC to embedded.
Speakers
avatar for Greg Favor

Greg Favor

CTO, Ventana Micro Systems
Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing... Read More →
Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)
  HPC / Data Center

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