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October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 12:10pm - 12:28pm PDT
A set of RISC-V Trace specifications developed by N-Trace TG has been recently ratified. It consists of three separated, but interconnected specifications: * RISC-V N-Trace (Nexus based) Trace Specification * RISC-V Trace Control Specification * RISC-V Trace Connectors Specification This session will explain key trace concepts and solutions. Relations to different existing trace standards will be highlighted. Practical use-cases, implementation hints and difficulties will be elaborated. Future development and possible enhancements will be mentioned.
Speakers
JG

Jay Gamoneda,

Front-End SoC Design Engineer, NXP
Nexus Trace encoders for RISC-V cores.SoC architecture including debug trace components.
avatar for Robert Chyla

Robert Chyla

Senior Staff Engineer (Debug and Trace), MIPS
My early engagement (Poland) included parallel programming. Later high-end computer graphics (Japan) with performance focus. In 1996 engaged with a embedded debug & trace probe vendor (California) and as VP of R&D I designed trace probes and tools. At the first RISC-V Summit I felt... Read More →
Wednesday October 23, 2024 12:10pm - 12:28pm PDT
Grand Ballroom H (Level 1)
  HPC / Data Center
  • Audience Experience Level Any

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