RISC-V Summit

During this session the attendees will learn about the goals, proposals, and status of the High Assurance Cryptography (HAC) Instruction Set Extension (ISE) for RISC-V vector CPUs. While overlapping the functionality of the ratified vector cryptography extensions somewhat, the HAC extensions will provide for better key management – including key encryption – and the possibility for microarchitectures to implement countermeasures against side-channel analysis, thus enabling the HAC instructions to provide secure cryptography in more use cases than the existing instructions. For example, when an adversary can gain close enough physical proximity to the CPU to monitor its electromagnetic emanations during operation, side-channel countermeasures are necessary for secure cryptographic implementations.

What may be of extra interest is that Barry Spinney, an active HAC task group member, is designing a proof-of-concept design of the core cryptographic functional unit, including the optional side-channel countermeasures, and intends to make it fully publicly available as open-source code. This talk will introduce Barry’s design to the audience.