RISC-V Summit

Optimizing Image Signal Processing with RISC-V FPGA - Umer Imran &Bilal Zafar, 10xEngineers
In this session, we will explore the successful implementation of Infinite-ISP, a comprehensive Image Signal Processor (ISP) development platform, on an Efinix FPGA leveraging a RISC-V core. Infinite-ISP provides a full-stack solution, from algorithm development to RTL design, FPGA/ASIC implementation, and associated firmware and tools, creating a unified platform that accelerates ISP development. Our case study will delve into the technical details of integrating Infinite-ISP with a RISC-V based FPGA, highlighting the challenges faced and the innovative solutions devised to overcome them. Attendees will learn about the performance benchmarks achieved and the significant enhancements in efficiency and scalability. Additionally, we will discuss the broader implications of using an open-source RISC-V architecture in specialized applications like ISP development. Join us to discover how leveraging RISC-V for ISP development can open new possibilities in image processing technology. This presentation is ideal for engineers, developers, and decision-makers interested in the cutting-edge intersection of RISC-V and image signal processing.

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores - Tammo Mürmann & Florian Meisel, Technical University of Darmstadt
Custom instruction set architecture extensions (ISAX) are an energy-efficient and cost-effective way to accelerate modern workloads. However, exploring different combinations of base cores and ISAXes for a specific application requires automation and a level of portability across microarchitectures not provided by existing approaches.
To that end, we present an end-to-end flow for ISAX specification, generation, and integration into a number of host cores with a range of different microarchitectures. For ISAX specification, we leverage CoreDSL, an open-source C-like behavioral architecture description language. Hardware generation is handled by Longnail, a domain-specific high-level synthesis tool that compiles CoreDSL specifications into hardware modules compatible with the open-source SCAIE-V extension interface, which we use for automatic integration into the host cores.
We demonstrate our tooling by generating ISAXes using a mix of features, including complex multi-cycle computations, memory accesses, branch instructions, custom registers, and decoupled execution across five MCUs and two application-class cores, and evaluate the quality of results on a 22nm ASIC process.

RISC-V & Its Role in Silicon Lifecycle Management - Vivek Chickermane, Siemens EDA
This session will focus on the use of RISC-V processors and the RISC-V Trace specification in safety critical applications and the ability to implement embedded solutions that serve as a foundation for a comprehensive SoC Silicon debug and continuous monitoring system.

Introduction of Deploying the Rv64ilp32 ABI on the Kendryte K230d for Productization - Ren Guo, Alibaba XuanTie
Over the past year, the Alibaba XuanTie and PLCT teams have been dedicated to promoting the rv64ilp32 ABI, as it effectively addresses the need to run ILP32 software on existing RVA Profiles. Unlike before, the RISC-V 64ilp32 ABI steers clear of the Linux userspace scenario, focusing instead on underlying software such as the Linux kernel, RTOS, firmware, and hypervisors. We completed the first productized SDK based on the rv64ilp32 ABI on Canaan's k230d chip, enabling rv64ilp32 Nuttx and Linux. The k230d is Canaan Kendryte's new product, a repackaged chip based on k230 that incorporates 128MB of internal memory to reduce costs. Thus, there is a strong demand for the ILP32 ABI. This presentation will demonstrate the advantages of rv64ilp32 through actual test data on the k230d EVB: it avoids a 30% waste of memory footprint and significantly improves the performance of Linux linked list traversal. We innovated sign-extend addressing to replace the traditional zero-extend addressing. The newer XuanTie processors support a new relaxed-extend addressing mode to gain more performance. Finally, the presentation will share progress and plans for the rv64ilp32 ABI on Embedded Hypervisors.