Name: HPC & Data Center Poster Sessions
Start: 2024-10-22T15:35:00-0700
End: 2024-10-22T16:15:00-0700

October 22-23, 2024
Santa Clara, CA
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Tuesday October 22, 2024 3:35pm - 4:15pm PDT

Expo Hall - Exhibit Hall A (Level 1)

Implementing and Verifying RISC-V Nexus Trace Compliant Trace Encoder for High Performance Cores - Sajosh Janarthanam, Tenstorrent Inc.
In this poster, we present the N-trace infrastructure, which supports instruction tracing for multiple out-of-order RISC-V cores. We discuss the architectural and microarchitectural decisions involved in designing the Encoder. Furthermore, we describe the infrastructure established to facilitate efficient trace transmission. Finally, we discuss the strategies employed to verify the Encoder and its associated components.

Speakers

Sajosh Janarthanam

Principal Engineer, Tenstorrent Inc.

Sajosh has over 20 years of experience in the semiconductor industry, participating in various stages of chip design, from microarchitecture development to post-silicon debug. Currently at Tenstorrent, he is working on RISC-V CPUs and AI SoCs that scale to meet different PPA (Power/Performance/Area... Read More →

Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Expo Hall - Exhibit Hall A (Level 1)

Poster Sessions, HPC + Data Center

RISC-V Summit

Sajosh Janarthanam

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