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RISC-V Summit has ended
October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 3:55pm - 4:40pm PDT
RISC-V has seen amazing growth in recent years across a range of applications, with one of the most exciting being High Performance Computing (HPC) where raw computational horsepower is used by scientists and engineers to tackle some of the biggest problems we face worldwide, including weather forecasting and designing more fuel efficient aircraft engines. The possibilities are endless, especially with recent advances in AI enabling new workloads and applications. RISC-V can accelerate the HPC community by providing many more opportunities for compute specialization,  delivering increased choice around the architecture, with CPUs tuned for specific workloads, and benefits around integration of accelerators. In this panel we will discuss the huge potential of RISC-V for HPC and how we are making the first generation of RISC-V based supercomputers.
Moderators
avatar for Andrew Moore

Andrew Moore

Director of Marketing, RISC-V International
Speakers
avatar for Luisa Gonzalez

Luisa Gonzalez

Research Scientist, Lawrence Berkeley National Laboratory
Dr. Patricia Gonzalez-Guerrero is a Research Scientist at Lawerence Berkeley National Laboratory. Her work spans ultra-low-power digital and mixed-signal SoC/ASIC/VLSI design for conventional and non-conventional forms of signal processing. She has also worked with FPGA and RISCV... Read More →
avatar for Nick Brown

Nick Brown

Senior Research Fellow, EPCC at the University of Edinburgh
Dr Nick Brown is a Senior Research Fellow at EPCC, the University of Edinburgh. His main interest is in the role that novel hardware can play in future supercomputers, and is specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively... Read More →
avatar for Travis Lanier

Travis Lanier

Chief Product Officer, Ventana Micro Systems
Travis Lanier is the Chief Product Officer at Ventana with over 28 years of experience in CPU development. He began his career at AMD, where worked on the K5, K6, and Athlon processors. He then spent over a decade at Arm, where he worked in both engineering and product management... Read More →
avatar for Wei-Han Lien

Wei-Han Lien

Chief CPU Architect and Fellow in Machine Learning hardware architecture, Tenstorrent Inc.
Wei-han Lien is a Chief CPU Architect and Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory sub-system for the Tenstorrent heterogeneous high-performance... Read More →
Wednesday October 23, 2024 3:55pm - 4:40pm PDT
Mission City Ballroom B2 - B5 (Level 1)
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