RISC-V Summit

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RISC-V Summit

October 22-23, 2024
Santa Clara, CA
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1:55pm PDT

Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here - Jin Kim, Esperanto Technologies Grand Ballroom G (Level 1)

2:15pm PDT

Building Tool Chains for RISC-V AI Accelerators - Jeremy Bennett, Embecosm Grand Ballroom G (Level 1) An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications - Jamie Kim, Samsung Electronics Grand Ballroom H (Level 1) RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS Theater (Level 2)

2:35pm PDT

LLM Inference on RISC-V Embedded CPUs - Yueh-Feng Lee, Andes Technology Grand Ballroom G (Level 1) Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android - Lev Rumyantsev & Jeremiah Griffin, Google Grand Ballroom H (Level 1)

3:15pm PDT

Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension - Markku-Juhani O. Saarinen, Tampere University Grand Ballroom H (Level 1) Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm Theater (Level 2)

11:50am PDT

RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc. Grand Ballroom H (Level 1) RISC-V Control-Flow Integrity (CFI) - Ved Shanbhogue, Rivos & George Christou, Technical University of Crete Theater (Level 2)

12:10pm PDT

Exploration of Productization of Android on RISC-V - Han Mao, Alibaba Damo Academy Grand Ballroom G (Level 1)

1:55pm PDT

GPU Program Support on RISC-V GPU - Hyesoon Kim, Georgia Tech Grand Ballroom G (Level 1)

2:15pm PDT

RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems Grand Ballroom H (Level 1) Hardening Linux and FreeBSD on RISC-V with CHERI - Carl Shaw, Codasip Theater (Level 2) Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs - Jon Taylor, Synopsys Grand Ballroom G (Level 1)

2:35pm PDT

Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers Grand Ballroom H (Level 1) Porting SLEEF to RISC-V - Ludovic Henry, Rivos & Eric Love, SiFive Grand Ballroom G (Level 1)