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October 22-23, 2024
Santa Clara, CA
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Monday October 21, 2024 9:30am - 9:55am PDT
The specification of the IOPMP, I/O Physical Memory Protection Unit, is nearing stability, making it an opportune moment to introduce the IOPMP programming model to users. This presentation will demonstrate the bottom-up programming model of IOPMP in M-mode, H-mode, and VS/S-mode.
In M mode, we utilize a native library, libiopmp, while H/S/VS-mode employs the SBI for IOPMP with necessary security checks. Within libiopmp, we will explore how to group the regions of a specific device into a memory domain, which can be easily switched and shared. This clarifies why IOPMP prefers the per-device association programming model over ARM's per-rule association model.

The SBI, positioned above the libiopmp, allows the other modes to manipulate the IOPMP. A hypervisor should be able to allocate devices for a guest OS. IOPMP's memory domain offers a convenient method for associating devices with a specific guest OS.

In H/S mode, hot-plug devices may necessitate IOPMP updates. In VS mode, a guest OS typically lacks knowledge about the physical memory, so the IOPMP's updates are generally transparent. Software in the higher privileged modes helps to manipulate IOPMP(s) behind guest OS requests.
Speakers
avatar for Paul Ku

Paul Ku

Deputy Technical Director, Andes Technology
Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. Besides, in the RISC-V International, he served the TEE Task Group as the vice-chair in 2021 and has been the chair of the IOPMP TG since 2022. He ever worked for Faraday Technology... Read More →
Monday October 21, 2024 9:30am - 9:55am PDT
Grand Ballroom H (Level 1)

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