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The Performance Analysis SIG works to improve the state of performance analysis on RISC-V systems, by overseeing both the development of new ISA extensions to improve visibility, and the enabling of the software ecosystem (firmware, OS, tools). In this talk, chair Beeman Strong and member Atish Patra will recap the work completed in the last year, including 4 new ISA extensions and several improvements to Linux perf, and introduce some ongoing work. This will include progress updates on the Performance Events TG, the Performance Event Sampling TG, the Self-hosted Trace TG, and further Linux kernel/perf tool enhancements that aim to allow performance analysis on RISC-V to match or exceed the experience on competing ISAs.
Beeman Strong is lead architect for CPU performance monitoring, debug, and trace at Rivos Inc. Prior to that he spent 25 years working at Intel, with the last 11 working on ISA definition with a focus on performance monitoring & trace. In that role he worked closely with software... Read More →
Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.
