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RISC-V Summit has ended
October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 11:30am - 11:48am PDT
Historically, software developers have been forced to use special compiler switches to instrument code to gather traces and performance information. This has three disadvantages: it requires recompilation of the code to include the instrumentation, it increases code size, and it affects/distorts execution timing of the program. SiFive has developed a new approach, SiFive® Event Trace. Event Trace is unique in that it provides front-end hardware filtering to selectively capture specific events as the RISC-V core executes programs in real time. No software instrumentation or recompilation is required, saving development and debug time while avoiding the overhead and timing distortion that can result from software instrumentation. SiFive Event Trace is flexible, allowing developers to choose events to capture, including calls/returns, exceptions, interrupts, context changes, watchpoints, external triggers, and more. Each trace event has a high-resolution timestamp that provides both duration and interval timing, and This session will give developers a complete overview of this innovative profiling solution and demonstrate how to configure, view, and interpret Event Traces
Speakers
avatar for Carsten Gosvig

Carsten Gosvig

Developer Tools Engineer, SiFive Inc
Carsten Gosvig is a Developer Tools Engineer at SiFive, heading the Debug, Trace and Profiling SW effort which includes the FreedomStudio (IDE), OpenOCD (JTAG) and GDB SW stack.
Wednesday October 23, 2024 11:30am - 11:48am PDT
Grand Ballroom G (Level 1)
  Software
  • Audience Experience Level Advanced
  • Session Slides Attached Yes
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