Name: Demo: Andes ACE: Enabling Custom RISCV Instructions Safely - Darren Jones, Andes Technology
Start: 2024-10-23T11:10:00-0700
End: 2024-10-23T11:20:00-0700

October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 11:10am - 11:20am PDT

Expo Hall - Exhibit Hall A - Demo Theater

One promise of RISC-V is that it enables Architects, Systems Designers, and SW Developers to add custom instructions. However, if you don’t have your own CPU design team, how do you do this without breaking the RISC-V standard part of the pipeline? This talk will describe how the Andes Custom Extensions (ACE) enables simple and safe insertion of custom instructions while enabling software development and performance modeling.

Speakers

Darren Jones

Solution Architect, Andes Technology

Darren started his career designing MIPS processors. From there, he transitioned to building large SOC’s utilizing ARM processor IP. More recently, he was VP of VLSI at two RISC-V startups building huge SOC’s for machine learning and AI. He is now a Solution Architect at Andes... Read More →

Wednesday October 23, 2024 11:10am - 11:20am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

about Darren started his career designing MIPS processors. From there, he transitioned to building large SOC’s utilizing ARM processor IP. More recently, he was VP of VLSI at two RISC-V startups building huge SOC’s for machine learning and AI. He is now a Solution Architect at Andes Technology leveraging his CPU and SOC experience to help systems designers solve their unique problems using innovative IP.

RISC-V Summit

Darren Jones

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