Loading…
Attending this event?
October 22-23, 2024
Santa Clara, CA
View More Details & Registration

The Sched app allows you to build your schedule but is not a substitute for your event registration. You must be registered for RISC-V Summit to participate in the sessions. If you have not registered but would like to join us, please go to the event registration page to purchase a registration.
Tuesday October 22, 2024 12:55pm - 1:05pm PDT
In this presentation, we will provide an overview of Ashling’s TraceLLM which offers unprecedented insights into your program’s real-time behavior through an intelligent trace capture and AI LLM based analysis software engine which can be queried using a natural language, prompt-based interface. TraceLLM, which works with the Ashling Vitra-XS hardware trace probe and RiscFree software debugger has the capability to understand the entire program execution flow and can answer any questions related to the program execution in a natural language and provide quick and accurate responses, substantially bringing down the time spent by developers for debugging. Dive into your program's behavior and watch as the intelligent engine examines the captured trace and delivers unprecedented insights including pinpointing potential bottlenecks, performance issues and offering actionable insights. Enhance efficiency, accelerate problem solving, and harness the full potential of your RISC-V systems with Ashling’s TraceLLM today.
Speakers
avatar for Rejeesh Shaji Babu

Rejeesh Shaji Babu

VP of Engineering, Ashling
Rejeesh Shaji babu is Ashling’s VP of Engineering with a BTech in Electronics and over sixteen years’ experience in Real-time Embedded Systems with a particular emphasis on Embedded Development Tools and Debugging. 
Tuesday October 22, 2024 12:55pm - 1:05pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Sign up or log in to save this to your schedule, view media, leave feedback and see who's attending!

Share Modal

Share this link via

Or copy link