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October 22-23, 2024
Santa Clara, CA
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Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Version 1.0.0 of the RISC-V Vector Cryptography extensions specification was ratified in late 2023 and adds high-performance cryptography operations to the comprehensive list of ISA features that RISC-V officially supports. We present the first open-source implementation of the RISC-V Vector Cryptography specification, using the PULP Project's Ara vector processor as a baseline and targeting a 28nm technology node. We present the design/verification opportunities and challenges that were encountered. Furthermore, a detailed review of the implementation and benchmarking results will be included in the presentation.
Speakers
avatar for Markku-Juhani O. Saarinen

Markku-Juhani O. Saarinen

Professor of Practice, Tampere University
Markku-Juhani O. Saarinen is a Professor of Practice (työelämäprofessori) at Tampere University (Finland). A cryptographer by training and with a long international career in security engineering, Markku has co-authored many of the ratified RISC-V cryptography extensions. Currently... Read More →
Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Grand Ballroom H (Level 1)

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