Name: Member Day Session: Verifying a CPU with Sail - Tim Hutt, Codasip
Start: 2024-10-21T11:00:00-0700
End: 2024-10-21T11:25:00-0700

October 22-23, 2024
Santa Clara, CA
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Monday October 21, 2024 11:00am - 11:25am PDT

Grand Ballroom H (Level 1)

How Codasip verified a configurable CPU using the open source RISC-V Sail model.

Speakers

Tim Hutt

Senior Verification Engineer, Codasip

I'm originally a mechanical engineer (I used to work on hair dryers for Dyson!) but via a meandering path found myself in the RISC-V verification world 18 months ago. I have worked on verifying Codasip's A730 chip, including setting up our integration with the Sail model and upstreaming... Read More →

Monday October 21, 2024 11:00am - 11:25am PDT
Grand Ballroom H (Level 1)

Member Day

RISC-V Summit

Tim Hutt

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