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October 22-23, 2024
Santa Clara, CA
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Tuesday October 22, 2024 1:05pm - 1:15pm PDT
As RISC-V adoption grows, how are EDA tools and IP adapting to address new and evolving design challenges? From architecture exploration to design implementation and software development, SoC designers are looking for ways to take advantage of the RISC-V ecosystem and deliver optimized products with fast time-to-market.  At Synopsys, we’re building RISC-V solutions to help customers from the beginning of the project to delivery and deployment, supporting the full RISC-V ISA plus custom instructions while enabling architecting of workload-optimized processors, comprehensive processor verification, and pre-silicon software development. Whether you are building your own RISC-V core, using a partner’s core, or implementing Synopsys ARC-V processor IP,  Synopsys can help you meet your project requirements.  This presentation will provide an overview of the broad range of Synopsys RISC-V solutions that have been proven by our customers taking RISC-V SoCs to silicon.
Speakers
avatar for Larry Lapides

Larry Lapides

Sr. Dir. Product Management, Synopsys
Larry Lapides is the Executive Director of Business Development at Synopsys, responsible for ImperasDV RISC-V processor verification products.  He came to Synopsys through the acquisition of Imperas, where he was a founding member and VP Worldwide Sales and Marketing. Larry has also... Read More →
Tuesday October 22, 2024 1:05pm - 1:15pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

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