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October 22-23, 2024
Santa Clara, CA
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Monday October 21, 2024 11:30am - 11:55am PDT
The Packed-SIMD specification (P spec) is critical and integral in expanding the RISC-V ecosystem in the MCU domain and will further the development of higher value applications needing cost-efficient processing of small data parallelism for audio, voice, sound, small images, slow video, tinyML, consumer electronics, and more. 

Processors which support DSP functionality are usually used to measure, filter, or compress continuous real-world analog signals. Although many DSP algorithms can be executed on a general-purpose CPU, there will be an unacceptable loss in performance for these time-critical applications. One could use the RISC-V vector extension to greatly improve performance of these algorithms, but the vector unit is typically an order of magnitude larger than a processor which implements the P specification. 

This presentation will provide an overview of the specification, benchmarking numbers, development tools, and task group status.
Speakers
avatar for Rich Fuhler

Rich Fuhler

Technical Director, Andes Technology
Monday October 21, 2024 11:30am - 11:55am PDT
Grand Ballroom H (Level 1)

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