RISC-V Summit

Commercializing CHERI on a Codasip A730 RISC-V Application Core - Tariq Kurd, Codasip
Memory safety continues to cause widespread and costly cyber security problems. Data breaches often arise from memory safety vulnerabilities leading to multi-million dollar losses for victims; for example, losses due to the well-known OpenSSL Heartbleed bug are estimated to exceed $500 million. Therefore, there is increasing interest in the Capability Hardware Enhanced RISC Instructions (CHERI) which is an ISA extension that mitigates memory safety vulnerabilities by design. CHERI has been primarily a research project until now! The University of Cambridge, which originated the technology, partnered with Codasip to propose a CHERI extension for RISC-V. Codasip also unveiled the first commercial implementation of a CHERI RISC-V: the A730 processor. In this poster, we introduce the A730 processor microarchitecture and highlight the main challenges to supporting CHERI RISC-V. We also describe the key differences between A730 implementations with and without CHERI support. In our experience, the A730 with CHERI is about 4% larger in area than an A730 without CHERI.

CHERI RISC-V Standardization - Peter Rugg, University of Cambridge
CHERI is a cross-architecture security technology, adding memory safety and compartmentalization features via capability support in the hardware. This poster will present the current effort to standardize the architectural extensions required to obtain these benefits in RISC-V: currently an effort shared by University of Cambridge, Codasip, Google, and others. The standardization work has been proceeding at pace, with a concrete specification document available, and extensive community interaction to iron out edge cases and ensure applicability to a wide range of uses.

The CHERI Alliance – Getting the Industry Together to Tackle a $10T / Year Problem - Mike Eftimakis, CHERI Alliance
Cybercrime costs the World more than $10T / year, and this amount is growing at an alarming rate. A study of software vulnerabilities has shown that over the past 20 years, memory attacks represented more than 70% of them. CHERI technology has been developed to solve the problem and has been proven to work. After 14 years of research and prototyping, CHERI is now ready to get out of the lab! A new CHERI SIG has been formed in RISC-V International, but adoption won’t happen without a significant industry-led effort: this is the goal of the CHERI Alliance.