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October 22-23, 2024
Santa Clara, CA
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Monday October 21, 2024 9:00am - 9:25am PDT
For RISC-V to be successful, industry confidence in the quality of produced cores is critical, driving the mission of the RISC-V International Certification Steering Committee (CSC). It is recognized that a high degree of commercial-grade testing is required, leveraging tests from verification specialists, as well as existing work. The CSC has noted the need for small and large core certification, as well as the SoC components around them.

This presentation will analyze the CSC requirements and detail the types of tests that are likely be required, given the focus on architectural analysis that goes much further than basic ISA compliance. We will discuss the kind of scenarios to be validated, and how this can best be accomplished using the required self-checking content. The certification tests could also form the foundation of a comprehensive microarchitectural verification suite. While this is not the goal of certification, we will demonstrate how this might benefit overall verification.

Attendees will gain a greater understanding of the implementation of a certification flow as part of a broader verification approach, and the impact on this on their cores or SoCs.
Speakers
avatar for Adnan Hamid

Adnan Hamid

President & CTO, Breker Verification Systems, Inc.
Adnan Hamid is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System... Read More →
Monday October 21, 2024 9:00am - 9:25am PDT
Theater (Level 2)

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