9:00am • Applications & Tools Horizontal Committee Meeting
9:30am • Member Day Session: Exploring the Programming Model of the RISC-V IOPMP - Paul Ku, Andes Technology
10:00am • Member Day Session: CHERI 101 and Standardization Session - Tariq Kurd, Codasip
11:00am • Member Day Session: Verifying a CPU with Sail - Tim Hutt, Codasip
11:30am • Member Day Session: The Need for a Packed-SIMD Extension - Rich Fuhler, Andes Technology
12:00pm • Member Day Session: Sailing Toward a Single Source of Truth - Paul Clarke, Ventana Micro Systems & Derek Hower, Qualcomm
1:30pm • Marketing & Events Committee Meeting
2:30pm • Member Day Session: Update on Unified Discovery - Siqi Zhao, Alibaba Inc.
3:00pm • Member Day Session: Why Do We Need Yocto Project on RISC-V - Challenges and Best Practices - Khem Raj, Comcast
3:30pm • Member Day Session: A Simple Plan: An API and ABI for Managing Multiple Distinct Sets of Custom Extensions - Guy Lemieux, University of British Columbia
4:00pm • Member Day Session: High Assurance Cryptography ISE - G. Richard Newell, Microchip Technology Inc.
9:00am • Member Day Session: Realizing RISC-V Certification, and What it Means for your Verification - Adnan Hamid, Breker Verification Systems
9:30am • Member Day Session: RISC-V for HPC: Where We Currently are and Where We Need to Go - Nick Brown, University of Edinburgh
10:00am • Member Day Session: Improving Performance Analysis on RISC-V - Beeman Strong & Atish Patra, Rivos, Inc
11:00am • Security Horizontal Committee Update - Andrew Dellow, Qualcomm & Ravi Sahita, Rivos Inc.
11:30am • Security Model Update - Nicholas Wood, Imagination Technologies
12:00pm • SOC Infrastructure Horizontal Committee Update - Ved Shanbhogue, Rivos Inc.
1:30pm • Unprivileged ISA Committee Update - Earl Kilian, Aril Inc.
2:00pm • Restarting the Automotive SIG - Andrea Gallo, RISC-V
2:30pm • Profiles Special Interest Group Update - David Weaver, Akeana & James Ball, Qualcomm
3:00pm • Privileged Software Horizontal Committee Annual Update - Anup Patel, Ventana Micro Systems
3:30pm • Member Day Session: Enabling New Security Frontiers: Deep-dive into Implementing Confidential Computing on RISC-V - Ravi Sahita & Atish Patra, Rivos
4:00pm • Technical Steering Committee Meeting
5:00pm • Member Day Keynotes
10:50am • Demo: XuanTie RISC-V Hardware and Software Full-stack Technology - James Shi, Alibaba DAMO Academy
11:15am • Demo: Enabling Automotive Safety with Andes RISC-V IP - Marc Evans, Andes Technology
12:45pm • Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks - Carl Shaw, Codasip
12:55pm • Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine - Rejeesh Shaji Babu, Ashling
1:05pm • Demo: More Than Point Tools: RISC-V Solutions - Larry Lapides, Synopsys
3:40pm • Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics
3:50pm • Demo: Super-optimized Ubuntu and Open Source on RISC-V - Gordan Markuš, Canonical
4:00pm • Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V - Kelvin Low, Samsung Foundry
9:00am • Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International
9:20am • Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy
9:40am • Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA
10:00am • Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology
10:15am • Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys
10:30am • Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology
4:15pm • Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework
4:30pm • Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley
4:50pm • Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted Speers, Microchip; Calista Redmond, RISC-V
11:30am • Sail RISC-V: Status and Future Challenges - Alasdair Armstrong, University of Cambridge
11:50am • Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP
12:10pm • Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Technology Co., Ltd.
1:55pm • Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc.
2:15pm • RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS
2:55pm • Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys
3:15pm • Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm
11:30am • RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos
11:50am • RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc.
12:10pm • Ratified N-Trace Specifications - an Overview - Robert Chyla, MIPS & Jay Gamoneda, NXP
1:55pm • RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built - David Chen, Stream Computing
2:15pm • RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems
2:35pm • Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers
2:55pm • Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive - Vasanth Waran, MIPS
9:00am • Keynote: RISC-V State of the Union - Krste Asanović, Chief Architect, RISC-V International
9:20am • Keynote: RISC-V Security - Current Initiatives and Future Trends - Helena Handschuh, Technical Board Advisor
9:38am • Keynote: Launchpad
9:55am • Keynote Panel: The Future of AI and Security - Andrew Dellow, Qualcomm; Kris Murphy, NVIDIA; Pete Bernard, tinyML Foundation; Pete Warden, Useful Sensors Inc; Andrea Gallo, RISC-V International
10:30am • Keynote: Mobilizing the Open Source Software Ecosystem for RISC-V - Barna Ibrahim, Vice Chair of RISE Governing Board & Principal, Business Development at Rivos Inc.
3:55pm • Keynote Panel: The Future of High Performance Computing is RISC-V - Luisa Gonzales, Lawrence Berkeley National Laboratory; Nick Brown, EPCC at the University of Edinburgh; Wei-Han Lien, Tenstorrent Inc.
4:40pm • Keynote: Community Awards
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