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11:30am • RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos
11:50am • RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc.
12:10pm • Ratified N-Trace Specifications - an Overview - Robert Chyla, MIPS & Jay Gamoneda, NXP
1:55pm • RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built - David Chen, Stream Computing
2:15pm • RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems
2:35pm • Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers
2:55pm • Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive - Vasanth Waran, MIPS
9:00am • Keynote: RISC-V State of the Union - Krste Asanović, Chief Architect, RISC-V International
9:20am • Keynote: RISC-V Security - Current Initiatives and Future Trends - Helena Handschuh, Technical Board Advisor
9:38am • Keynote: Launchpad
9:55am • Keynote Panel: The Future of AI and Security - Andrew Dellow, Qualcomm; Kris Murphy, NVIDIA; Pete Bernard, tinyML Foundation; Pete Warden, Useful Sensors Inc; Andrea Gallo, RISC-V International
10:30am • Keynote: Mobilizing the Open Source Software Ecosystem for RISC-V - Barna Ibrahim, Vice Chair of RISE Governing Board & Principal, Business Development at Rivos Inc.
3:55pm • Keynote Panel: The Future of High Performance Computing is RISC-V - Luisa Gonzales, Lawrence Berkeley National Laboratory; Nick Brown, EPCC at the University of Edinburgh; Wei-Han Lien, Tenstorrent Inc.
4:40pm • Keynote: Community Awards