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10:50am • Demo: XuanTie RISC-V Hardware and Software Full-stack Technology - James Shi, Alibaba DAMO Academy
11:15am • Demo: Enabling Automotive Safety with Andes RISC-V IP - Marc Evans, Andes Technology
12:45pm • Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks - Carl Shaw, Codasip
12:55pm • Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine - Rejeesh Shaji Babu, Ashling
1:05pm • Demo: More Than Point Tools: RISC-V Solutions - Larry Lapides, Synopsys
3:40pm • Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics
3:50pm • Demo: Super-optimized Ubuntu and Open Source on RISC-V - Gordan Markuš, Canonical
4:00pm • Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V - Kelvin Low, Samsung Foundry
9:00am • Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International
9:20am • Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy
9:40am • Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA
10:00am • Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology
10:15am • Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys
10:30am • Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology
4:15pm • Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework
4:30pm • Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley
4:50pm • Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted Speers, Microchip; Calista Redmond, RISC-V
11:30am • Sail RISC-V: Status and Future Challenges - Alasdair Armstrong, University of Cambridge
11:50am • Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP
12:10pm • Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Technology Co., Ltd.
1:55pm • Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc.
2:15pm • RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS
2:55pm • Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys
3:15pm • Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm
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