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9:00am PDT
9:30am PDT
10:00am PDT
11:00am PDT
Security Horizontal Committee Update - Andrew Dellow, Qualcomm & Ravi Sahita, Rivos Inc.
Monday October 21, 2024 11:00am - 11:25am PDT
Speakers
Director of Engineering, Qualcomm & Chair, RISC-V Security HC, Qualcomm
Principal Security Architect, Rivos Inc.
Ravi Sahita is a Principal Security Architect at Rivos Inc, and vice-chair of the Security HC at RVI. He is an expert in ISA/platform virtualization, trusted execution, and exploit prevention. In past work, he led the security arch. for confidential computing on x86 servers, exploit...
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11:30am PDT
12:00pm PDT
SOC Infrastructure Horizontal Committee Update - Ved Shanbhogue, Rivos Inc.
Monday October 21, 2024 12:00pm - 12:25pm PDT
Speakers
Member of Technical Staff, Rivos Inc.
Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure...
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1:30pm PDT
2:00pm PDT
2:30pm PDT
3:00pm PDT
3:30pm PDT
Member Day Session: Enabling New Security Frontiers: Deep-dive into Implementing Confidential Computing on RISC-V - Ravi Sahita & Atish Patra, Rivos
Monday October 21, 2024 3:30pm - 3:55pm PDT
Speakers
Principal Security Architect, Rivos Inc.
Ravi Sahita is a Principal Security Architect at Rivos Inc, and vice-chair of the Security HC at RVI. He is an expert in ISA/platform virtualization, trusted execution, and exploit prevention. In past work, he led the security arch. for confidential computing on x86 servers, exploit...
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Linux kernel Engineer, Rivos Inc.
Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.
5:00pm PDT
11:30am PDT
11:50am PDT
Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP
Tuesday October 22, 2024 11:50am - 12:08pm PDT
Speakers
Senior Principal RISC-V Architect, NXP Semiconductors Germany GmbH
Christian Herber is a Senior Principal RISC-V Architect at NXP, working on innovation management and technical roadmaps for RISC-V processors. He led several specification efforts, e.g. the "Load/Store Pair for RV32" RISC-V fast-track extension and the "OpenHW Group Core-V Extension...
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12:10pm PDT
1:55pm PDT
2:15pm PDT
RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS
Tuesday October 22, 2024 2:15pm - 2:53pm PDT
Speakers
Sr. Principal Engineer, MIPS
Sr. Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. Lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians and co-chair of the RISC-V International Performance Modeling SIG
2:55pm PDT
Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys
Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Speakers
Sr. Dir. Product Management, Synopsys
Aimee is currently Sr. Dir. Product Management at Synopsys, responsible for solutions for RISC-V processor verification and system test generation. She has been involved in the design verification space for over 20 years, as both an EDA tool user and EDA tool developer, with Imperas...
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Sr. Director, Applications Engineering, Synopsys
Xiaolin Chen is a Sr. Director of Applications Engineering, formal solutions at Synopsys. She leads a team of applications engineers providing guidance, training, assistance and consulting to semiconductor customers to successfully develop formal technology in verification flow. The...
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3:15pm PDT
Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm
Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Speakers
Chief Executive, Embecosm
Bio: Dr Jeremy Bennett is founder and Chief Executive of Embecosm(http://www.embecosm.com), a consultancy implementing open sourcecompilers, chip simulators and AI/ML for major corporations around the world.He is a author of the standard textbook "Introduction to CompilingTechniques...
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Staff Software Architecture Engineer, SiFive
Max Chou is a Staff Software - Systems Development Engineer at SiFive. His research interests include binary translation, debugging, optimizations, performance and program analysis tools.
11:30am PDT
Software Engineers Are Tomorrow's Processor Engineers - Keith Graham, Codasip
Wednesday October 23, 2024 11:30am - 11:48am PDT
Speakers
VP of University Program, Codasip
Over my thirty-nine-year career, I've gone from designing workstations, developing multi-processor cache and memory management units, selling semiconductors, small business owner, senior instructor teaching embedded systems and computer architecture, to leading Codasip's University...
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11:50am PDT
RISC-V Control-Flow Integrity (CFI) - Ved Shanbhogue, Rivos & George Christou, Technical University of Crete
Wednesday October 23, 2024 11:50am - 12:28pm PDT
Speakers
Member of Technical Staff, Rivos Inc.
Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure...
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Technical University of Crete
George Christou received his BSc in Computer Science from the University of Crete. His MSc thesis was the design and implementation of hardware assisted Control Flow Integrity for Sparc V8 architecture. His PhD under the supervision of Prof. Sotiris Ioannidis is titled "Hardware-Assisted...
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1:55pm PDT
2:15pm PDT
Hardening Linux and FreeBSD on RISC-V with CHERI - Carl Shaw, Codasip
Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Speakers
Safety and Security Manager, Codasip
Prior to joining Codasip, Carl has provided security engineering and architecture consultancy to leading global electronics and semiconductor companies for more than 15 years. With a Physics Ph.D., and a career mixing electronics design in government defense, and OS and firmware development...
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2:35pm PDT
2:55pm PDT
A Decade of Accelerating Adoption: RISC-V Market Analysis, From Now to 2031 - Rich Wawrzyniak, The SHD Group
Wednesday October 23, 2024 2:55pm - 3:13pm PDT
Speakers
Principal Analyst: ASIC, SoC & IP, The SHD Group
Rich Wawrzyniak brings to The SHD Group over 35 years of semiconductor industry experience, 20 of which were dedicated to market analysis at Semico Research Corp. Rich has excelled in roles from sales management to corporate planning, with an expertise in ASICs, SoCs, SIP, Memory...
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