RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
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9:00am PDT

Member Day Session: Realizing RISC-V Certification, and What it Means for your Verification - Adnan Hamid, Breker Verification Systems

Monday October 21, 2024 9:00am - 9:25am PDT

Theater (Level 2)

For RISC-V to be successful, industry confidence in the quality of produced cores is critical, driving the mission of the RISC-V International Certification Steering Committee (CSC). It is recognized that a high degree of commercial-grade testing is required, leveraging tests from verification specialists, as well as existing work. The CSC has noted the need for small and large core certification, as well as the SoC components around them.

This presentation will analyze the CSC requirements and detail the types of tests that are likely be required, given the focus on architectural analysis that goes much further than basic ISA compliance. We will discuss the kind of scenarios to be validated, and how this can best be accomplished using the required self-checking content. The certification tests could also form the foundation of a comprehensive microarchitectural verification suite. While this is not the goal of certification, we will demonstrate how this might benefit overall verification.

Attendees will gain a greater understanding of the implementation of a certification flow as part of a broader verification approach, and the impact on this on their cores or SoCs.

Speakers

Adnan Hamid

President & CTO, Breker Verification Systems, Inc.

Adnan Hamid is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System... Read More →

Monday October 21, 2024 9:00am - 9:25am PDT
Theater (Level 2)

Member Day

9:30am PDT

Member Day Session: RISC-V for HPC: Where We Currently are and Where We Need to Go - Nick Brown, University of Edinburgh

Monday October 21, 2024 9:30am - 9:55am PDT

Theater (Level 2)

The powerhouse which unlocks the ability to simulate complex, real world problems, as well as powering AI and ML workloads, High Performance Computing (HPC) is a crucial part of the modern day world. Supercomputers most commonly leverage x86 CPUs and Nvidia or AMD GPUs, however, as the ever-increasing demand by users for more capability meets a growing focus on sustainability, alternative technologies such as RISC-V are important.

RISC-V can offer benefits in performance and energy efficiency to HPC through the potential for specialisation, however the HPC community is yet to embrace RISC-V. But with increased availability of commodity RISC-V high performance CPUs (e.g. the SG2042) and PCIe accelerator cards, RISC-V is becoming a more serious option.

In the RISC-V HPC SIG our role to help drive adoption, and in this talk I will describe where the RISC-V ecosystem currently lies for HPC, explore performance and energy efficiency of latest generation RISC-V hardware against that currently more commonplace in HPC, and highlight key areas that we as the RISC-V community should prioritise to drive RISC-V adoption in HPC. Ultimately acting as a call to action for the RISC-V community.

Speakers

Nick Brown

Senior Research Fellow, EPCC at the University of Edinburgh

Dr Nick Brown is a Senior Research Fellow at EPCC, the University of Edinburgh. His main interest is in the role that novel hardware can play in future supercomputers, and is specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively... Read More →

Monday October 21, 2024 9:30am - 9:55am PDT
Theater (Level 2)

Member Day

10:00am PDT

Member Day Session: Improving Performance Analysis on RISC-V - Beeman Strong & Atish Patra, Rivos, Inc

Monday October 21, 2024 10:00am - 10:25am PDT

Theater (Level 2)

The Performance Analysis SIG works to improve the state of performance analysis on RISC-V systems, by overseeing both the development of new ISA extensions to improve visibility, and the enabling of the software ecosystem (firmware, OS, tools). In this talk, chair Beeman Strong and member Atish Patra will recap the work completed in the last year, including 4 new ISA extensions and several improvements to Linux perf, and introduce some ongoing work. This will include progress updates on the Performance Events TG, the Performance Event Sampling TG, the Self-hosted Trace TG, and further Linux kernel/perf tool enhancements that aim to allow performance analysis on RISC-V to match or exceed the experience on competing ISAs.

Speakers

Beeman Strong

Hardware Architect, Rivos Inc.

Beeman Strong is lead architect for CPU performance monitoring, debug, and trace at Rivos Inc. Prior to that he spent 25 years working at Intel, with the last 11 working on ISA definition with a focus on performance monitoring & trace. In that role he worked closely with software... Read More →

Atish Patra

Linux kernel Engineer, Rivos

Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.

Monday October 21, 2024 10:00am - 10:25am PDT
Theater (Level 2)

Member Day

11:00am PDT

Security Horizontal Committee Update - Andrew Dellow, Qualcomm & Ravi Sahita, Rivos Inc.

Monday October 21, 2024 11:00am - 11:25am PDT

Theater (Level 2)

Speakers

Andrew Dellow

Director of Engineering, Qualcomm & Chair, RISC-V Security HC, Qualcomm

Ravi Sahita

Principal Security Architect, Rivos Inc.

Ravi Sahita is a Principal Security Architect at Rivos Inc, and vice-chair of the Security HC at RVI. He is an expert in ISA/platform virtualization, trusted execution, and exploit prevention. In past work, he led the security arch. for confidential computing on x86 servers, exploit... Read More →

Monday October 21, 2024 11:00am - 11:25am PDT
Theater (Level 2)

Member Day

11:30am PDT

Security Model Update - Nicholas Wood, Imagination Technologies

Monday October 21, 2024 11:30am - 11:55am PDT

Theater (Level 2)

Speakers

Nicholas Wood

Security Architect, Imagination Technologies

Monday October 21, 2024 11:30am - 11:55am PDT
Theater (Level 2)

Member Day

12:00pm PDT

SOC Infrastructure Horizontal Committee Update - Ved Shanbhogue, Rivos Inc.

Monday October 21, 2024 12:00pm - 12:25pm PDT

Theater (Level 2)

Speakers

Ved Shanbhogue

Member of Technical Staff, Rivos

Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure... Read More →

Monday October 21, 2024 12:00pm - 12:25pm PDT
Theater (Level 2)

Member Day

1:30pm PDT

Unprivileged ISA Committee Update - Earl Kilian, Aril Inc.

Monday October 21, 2024 1:30pm - 1:55pm PDT

Theater (Level 2)

Speakers

Earl Kilian

CTO, Aril

Monday October 21, 2024 1:30pm - 1:55pm PDT
Theater (Level 2)

Member Day

2:00pm PDT

Restarting the Automotive SIG - Andrea Gallo, RISC-V

Monday October 21, 2024 2:00pm - 2:25pm PDT

Theater (Level 2)

Speakers

Andrea Gallo

VP of Technology, RISC-V

Monday October 21, 2024 2:00pm - 2:25pm PDT
Theater (Level 2)

Member Day

2:30pm PDT

Profiles Special Interest Group Update - David Weaver, Akeana & James Ball, Qualcomm

Monday October 21, 2024 2:30pm - 2:55pm PDT

Theater (Level 2)

Speakers

James Ball

Qualcomm

David Weaver

Principal Architect, Akeana

Monday October 21, 2024 2:30pm - 2:55pm PDT
Theater (Level 2)

Member Day

3:00pm PDT

Privileged Software Horizontal Committee Annual Update - Anup Patel, Ventana Micro Systems

Monday October 21, 2024 3:00pm - 3:25pm PDT

Theater (Level 2)

Speakers

Anup Patel

Principal Software Engineer, Ventana Micro Systems

Anup Patel is an open-source enthusiast with primary interest in hypervisors, firmwares, boot-loaders, and Linux kernel. He has 18+ years of experience developing system level software and he maintains various open-source projects such as OpenSBI, KVM RISC-V, and Xvisor. He is part... Read More →

Monday October 21, 2024 3:00pm - 3:25pm PDT
Theater (Level 2)

Member Day

3:30pm PDT

Member Day Session: Enabling New Security Frontiers: Deep-dive into Implementing Confidential Computing on RISC-V - Ravi Sahita & Atish Patra, Rivos

Monday October 21, 2024 3:30pm - 3:55pm PDT

Theater (Level 2)

This session aims to cover ISA and non-ISA for Confidential VM Environment (CoVE) on RISC-V platforms. The session will describe the use of ratified RISC-V privileged ISA extensions and new priv. ISA extensions called "Supervisor Domains" that are proposed and reaching task group consensus. This session will also describe the specifications for proposed non-ISA/ABI extensions and SoC requirements that enable Confidential Computing on RISC-V-based platforms - and the related open-source activities in open-source that are required to enable the confidential computing stack on RISC-V platforms. The common/abstract aspects that are cross-architectural will be discussed to enable interoperability across different RISC-V and non-RISC-V platforms. A future roadmap of capabilities will be discussed to encourage participation from the community.

Speakers

Ravi Sahita

Principal Security Architect, Rivos Inc.

Atish Patra

Linux kernel Engineer, Rivos

Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.

Monday October 21, 2024 3:30pm - 3:55pm PDT
Theater (Level 2)

Member Day

4:00pm PDT

Technical Steering Committee Meeting

Monday October 21, 2024 4:00pm - 4:25pm PDT

Theater (Level 2)

Monday October 21, 2024 4:00pm - 4:25pm PDT
Theater (Level 2)

Member Day

5:00pm PDT

Member Day Keynotes

Monday October 21, 2024 5:00pm - 6:00pm PDT

Theater (Level 2)

Member Day Closing Keynotes:

Welcome and remarks (Calista 15 min)
Marketing highlights (Andy or Marketing Chair 15 min)
Technical highlights (Krste or Greg/Philipp as Tech Chairs 20 min)
Community highlights (Megan 10 min)

Monday October 21, 2024 5:00pm - 6:00pm PDT
Theater (Level 2)

Member Day

11:30am PDT

Sail RISC-V: Status and Future Challenges - Alasdair Armstrong, University of Cambridge

Tuesday October 22, 2024 11:30am - 11:48am PDT

Theater (Level 2)

In this talk I will present ongoing work as part of the RISC-V golden model working group to develop and maintain the Sail language and golden reference model for the RISC-V ISA. Sail is an open-source domain-specific language for ISA design and definition, which supports many use-cases, including documentation, use as a reference simulator, relaxed-concurrency semantics, hardware verification, and more.

This talk will describe our vision for the future of the RISC-V golden model. There are many challenges faced by model developers, such as the vast ecosystem of extensions and configurable options supported by RISC-V. We also need to provide a model that is more broadly useful as a source of documentation and learning for the wider RISC-V community.
I will discuss solutions for these challenges, which we intend to address both within the golden model itself, and by co-evolving Sail language itself to better support the unique needs of RISC-V. For example, we are introducing a module system for organising RISC-V extensions, a unified configuration system that supports all the aforementioned Sail use-cases, and enhanced Asciidoctor support for documentation integration.

By presenting this talk, I also hope to be able to engage further with attendees regarding their needs from a golden model.

Speakers

Alasdair Armstrong

University of Cambridge

I'm currently a research associate at Cambridge University working with Prof. Peter Sewell. In addition to developing and maintaining the Sail language, most recently I have been working on symbolic execution and relaxed-memory concurrency for Sail models, as well as formal verification... Read More →

Tuesday October 22, 2024 11:30am - 11:48am PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Any

11:50am PDT

Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP

Tuesday October 22, 2024 11:50am - 12:08pm PDT

Theater (Level 2)

The Zilsd & Zclsd extensions provide load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings. The extensions are expected to be implemented in all kinds of embedded processors, with optimal performance being reached in core with a data bus of at least 64 bit - a property commonly given in superscalar implementations. The impact on code size of this extension is discussed in detail, leading to recommendations for future compiler improvements.

Speakers

Christian Herber

Senior Principal RISC-V Architect, NXP

Christian Herber is a Senior Principal RISC-V Architect at NXP, working on innovation management and technical roadmaps for RISC-V processors. He led several specification efforts, e.g. the "Load/Store Pair for RV32" RISC-V fast-track extension and the "OpenHW Group Core-V Extension... Read More →

Tuesday October 22, 2024 11:50am - 12:08pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Any

12:10pm PDT

Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Technology Co., Ltd.

Tuesday October 22, 2024 12:10pm - 12:28pm PDT

Theater (Level 2)

We introduce the practical applications and innovative explorations of RISC-V processors in the field of graphics processing.Especially the application of RVV in graphics acceleration.

Speakers

Siqi Zhao

Technology Expert, Alibaba DAMO Academy

Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community. He is currently serving... Read More →

Tuesday October 22, 2024 12:10pm - 12:28pm PDT
Theater (Level 2)

ISA and Design Tools

1:55pm PDT

Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc.

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Theater (Level 2)

Traditional post silicon HW debug data collection involves the gathering of a snapshot of the design state at the point of failure using scan and an array dump. We propose a hardware mechanism called Debug Signal Trace (DST) that provides the ability to trace a set of design signals over multiple cycles leading to the point of the failure and to store the trace to an on-chip memory like SRAM, or to off-chip System memory. Post processing of the stored debug trace data not only gives debug visibility, but also the ability to build post silicon coverage points. Debug Signal Trace data is timestamped to correlate with instruction trace data. This extends the use-case to SW performance analysis. To ease adoption and usability, the DST control register definition mirrors that of the RISC-V Trace Control Interface which is familiar to the RISC-V debug community. DST supports signal compression to minimize the memory storage footprint. DST leverages the triggers specified in RISC-V Debug Spec while adding user configurable triggers using a select set of design signals.

Speakers

Sajosh Janarthanam

Principal Engineer, Tenstorrent Inc.

Sajosh has over 20 years of experience in the semiconductor industry, participating in various stages of chip design, from microarchitecture development to post-silicon debug. Currently at Tenstorrent, he is working on RISC-V CPUs and AI SoCs that scale to meet different PPA (Power/Performance/Area... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Beginner

2:15pm PDT

RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS

Tuesday October 22, 2024 2:15pm - 2:53pm PDT

Theater (Level 2)

The RISC-V Foundation's Olympia Performance Model is a great tool as the basis for designing a high-performance RISC-V CPU design. This session will provide a high-level overview of the Olympia Performance Model and then provide examples of how to use the model for tradeoff analysis on different RISC-V Out-of-Order superscalar designs.

Speakers

Knute Lingaard

Sr. Principal Engineer, MIPS

Sr. Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. Lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians and co-chair of the RISC-V International Performance Modeling SIG

Tuesday October 22, 2024 2:15pm - 2:53pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

2:55pm PDT

Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys

Tuesday October 22, 2024 2:55pm - 3:13pm PDT

Theater (Level 2)

With the increased usage of RISC-V processors across the whole range of SoC market segments, quality of the RISC-V processor is an increasingly important issue. Historically, processor IP has been purchased from single-source vendors who own the ISA, and this IP was assumed to be of excellent quality. However, in the RISC-V ecosystem with vendor-supplied IP, open source IP and IP developed in-house, such quality cannot be taken for granted. This creates a verification “disconnect” between SoC developers expecting high-quality IP and processor developers that do not have the verification resources of the single source processor IP vendors. This talk will discuss how dynamic and formal methods can be used together for a more thorough and efficient verification process, helping to bridge the verification disconnect. Examples of using this combined methodology on open-source cores from OpenHW Group, specifically the CV32E40 family, CVW and CVA6, will be presented, including functional coverage results. A key feature of the RISC-V ISA is its extensibility, enabling custom instructions and CSRs to be added. The combined approach will also be shown to work well in this common situation.

Speakers

Aimee Sutton

Sr. Dir. Product Management, Synopsys

Aimee is currently Sr. Dir. Product Management at Synopsys, responsible for solution for RISC-V processor verification and system test generation. She has been involved in the design verification space for over 20 years, as both an EDA tool user and EDA tool developer, with Metrics... Read More →

Xiaolin Chen

Sr. Director, Applications Engineering, Synopsys

Xiaolin Chen is a Sr. Director of Applications Engineering, formal solutions at Synopsys. She leads a team of applications engineers providing guidance, training, assistance and consulting to semiconductor customers to successfully develop formal technology in verification flow. The... Read More →

Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Beginner

3:15pm PDT

Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Theater (Level 2)

QEMU is an emulator that developers can developer and debug their software on it before getting the real RISC-V hardware. We observed that vectorized executables run much slower than non-vectorized ones on QEMU. From benchmarks (e.g. SPEC CPU2k6 h264), we can see that most of the execution time is occupied by RVV load/store instructions. The same observation has been reported in the QEMU community. For example, the glibc memcpy benchmark runs 2x to 60x slower than its scalar equivalent on QEMU. We aim to improve the performance of RVV instructions in QEMU, thereby reducing the execution time required for tasks such as Android bootup. In this talk, we will provide an overview of how we enhanced the performance of QEMU RVV load/store instructions and discuss future work.

Speakers

Jeremy Bennett

Chief Executive, Embecosm

Bio: Dr Jeremy Bennett is founder and Chief Executive of Embecosm(http://www.embecosm.com), a consultancy implementing open sourcecompilers, chip simulators and AI/ML for major corporations around the world.He is a author of the standard textbook "Introduction to CompilingTechniques... Read More →

Max Chou

Engineer, SiFive

Max Chou is a Staff Software - Systems Development Engineer at SiFive. His research interests include binary translation, debugging, optimizations, performance and program analysis tools.

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

11:30am PDT

Software Engineers Are Tomorrow's Processor Engineers - Keith Graham, Codasip

Wednesday October 23, 2024 11:30am - 11:48am PDT

Theater (Level 2)

RISC-V's open standard provides a great opportunity to democratize the Domain Specific Processor market. Over the last twenty to thirty years, the processor market was dominated by general purpose closed-architectures. This environment limited processor engineering companies and job prospects. RISC-V enables a new going to market strategy that is not linked to a limited number of processor vendors, but a market strategy where the application and processor integrator defines and develops the Domain Specific Processor, the traditional System-On-Chip (SoC) developer. To extend custom processing to the larger segment of SoC developers, new processor engineers are required. Due to the lack of previous job prospects, there is a processor engineering shortage to sustain the pace of innovation. The RISC-V ecosystem is coming to the rescue. By developing processor Bounded Customization models where the Software Engineer uses standard software programming practices to architect and to develop custom processors, the inadequate supply of processor engineers can be solved. Who better than the application and algorithm engineer to become tomorrow's processor engineer.

Speakers

Keith Graham

VP of University Program, Codasip

Over my thirty-nine-year career, I've gone from designing workstations, developing multi-processor cache and memory management units, selling semiconductors, small business owner, senior instructor teaching embedded systems and computer architecture, to leading Codasip's University... Read More →

Wednesday October 23, 2024 11:30am - 11:48am PDT
Theater (Level 2)

Security

Audience Experience Level Any

11:50am PDT

RISC-V Control-Flow Integrity (CFI) - Ved Shanbhogue, Rivos & George Christou, Technical University of Crete

Wednesday October 23, 2024 11:50am - 12:28pm PDT

Theater (Level 2)

Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks. This session will provide an overview of how the recently ratified Zicfiss and Zicfilp extensions help defend the programs control flow.

Speakers

Ved Shanbhogue

Member of Technical Staff, Rivos

George Christou

Technical University of Crete

George Christou received his BSc in Computer Science from the University of Crete. His MSc thesis was the design and implementation of hardware assisted Control Flow Integrity for Sparc V8 architecture. His PhD under the supervision of Prof. Sotiris Ioannidis is titled "Hardware-Assisted... Read More →

Wednesday October 23, 2024 11:50am - 12:28pm PDT
Theater (Level 2)

Security

Audience Experience Level Intermediate

1:55pm PDT

Understanding the Unformated Trace & Diagnostic Data Packet Encapsulation for RISC-V Specification - Iain Robertson, Siemens EDA

Wednesday October 23, 2024 1:55pm - 2:13pm PDT

Theater (Level 2)

The Unformatted Trace and Diagnostic Data Packet Encapsulation for RISC-V specification was recently ratified. The standard was developed in response to a need for a standard encapsulation format for Efficient Trace for RISC-V (E-Trace) packets, that would support a variety of widely used transport protocols. However, the resulting standard is broader than this, and is suitable for encapsulating any kind of unformatted diagnostic data.

This presentation explores the properties and benefits of this standard and shows how it can be applied to E-Trace (as well as other types of diagnostic data such as bus utilization metrics, bus or logic analyzer trace and code profiling instrumentation) for transport via AMBA ATB or the Siemens Messaging Infrastructure.

Speakers

Iain Robertson

Senior Director, Hardware Engineering, Siemens EDA

Iain Robertson is Senior Hardware Engineering Director for Tessent Embedded Analytics, a productline within Siemens EDA. Iain has more than 35 years’ experience in silicon design, architecture andengineering team leadership. An expert in monitoring, analytics, processor trace and... Read More →

Wednesday October 23, 2024 1:55pm - 2:13pm PDT
Theater (Level 2)

Security

Audience Experience Level Beginner

2:15pm PDT

Hardening Linux and FreeBSD on RISC-V with CHERI - Carl Shaw, Codasip

Wednesday October 23, 2024 2:15pm - 2:33pm PDT

Theater (Level 2)

CHERI is an emerging security technology, jointly developed over the last decade by the University of Cambridge and SRI International. In this talk, we will describe the work being done to bring CHERI support to FreeBSD and Linux on RISC-V, where we can provide both memory safety as well as isolating software components to improve run-time safety, security and robustness.

Speakers

Carl Shaw

Safety and Security Manager, Codasip

Prior to joining Codasip, Carl has provided security engineering and architecture consultancy to leading global electronics and semiconductor companies for more than 15 years. With a Physics Ph.D., and a career mixing electronics design in government defense, and OS and firmware development... Read More →

Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Theater (Level 2)

Security

Audience Experience Level Intermediate

2:35pm PDT

Making the Case for a Keccak Instruction - Markku-Juhani O. Saarinen, Tampere University

Wednesday October 23, 2024 2:35pm - 2:53pm PDT

Theater (Level 2)

We will give the latest performance evaluation of the main Post-Quantum Cryptography standards, Kyber and Dilithium, on RISC-V Vector Architecture and discuss possibilities for speeding it up further with new instructions. Due to its 1600-bit state size, a fast SHA3 / Keccak instruction would require slightly unusual architectural features from a vector processor. Based on hardware and software experiments and benchmarks, we argue that performance returns in Post-Quantum Cryptography still make it worthwhile for many common use cases, such as content delivery servers performing a lot of TLS handshakes.

Speakers

Markku-Juhani O. Saarinen

Professor of Practice, Tampere University

Markku-Juhani O. Saarinen is a Professor of Practice (työelämäprofessori) at Tampere University (Finland). A cryptographer by training and with a long international career in security engineering, Markku has co-authored many of the ratified RISC-V cryptography extensions. Currently... Read More →

Wednesday October 23, 2024 2:35pm - 2:53pm PDT
Theater (Level 2)

Security

Audience Experience Level Advanced