RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
View More Details & Registration

The Sched app allows you to build your schedule but is not a substitute for your event registration. You must be registered for RISC-V Summit to participate in the sessions. If you have not registered but would like to join us, please go to the event registration page to purchase a registration.

9:00am PDT

Applications & Tools Horizontal Committee Meeting

Monday October 21, 2024 9:00am - 9:25am PDT

Grand Ballroom H (Level 1)

Monday October 21, 2024 9:00am - 9:25am PDT
Grand Ballroom H (Level 1)

Member Day

9:30am PDT

Member Day Session: Exploring the Programming Model of the RISC-V IOPMP - Paul Ku, Andes Technology

Monday October 21, 2024 9:30am - 9:55am PDT

Grand Ballroom H (Level 1)

The specification of the IOPMP, I/O Physical Memory Protection Unit, is nearing stability, making it an opportune moment to introduce the IOPMP programming model to users. This presentation will demonstrate the bottom-up programming model of IOPMP in M-mode, H-mode, and VS/S-mode.
In M mode, we utilize a native library, libiopmp, while H/S/VS-mode employs the SBI for IOPMP with necessary security checks. Within libiopmp, we will explore how to group the regions of a specific device into a memory domain, which can be easily switched and shared. This clarifies why IOPMP prefers the per-device association programming model over ARM's per-rule association model.

The SBI, positioned above the libiopmp, allows the other modes to manipulate the IOPMP. A hypervisor should be able to allocate devices for a guest OS. IOPMP's memory domain offers a convenient method for associating devices with a specific guest OS.

In H/S mode, hot-plug devices may necessitate IOPMP updates. In VS mode, a guest OS typically lacks knowledge about the physical memory, so the IOPMP's updates are generally transparent. Software in the higher privileged modes helps to manipulate IOPMP(s) behind guest OS requests.

Speakers

Paul Ku

Deputy Technical Director, Andes Technology

Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. Besides, in the RISC-V International, he served the TEE Task Group as the vice-chair in 2021 and has been the chair of the IOPMP TG since 2022. He ever worked for Faraday Technology... Read More →

Monday October 21, 2024 9:30am - 9:55am PDT
Grand Ballroom H (Level 1)

Member Day

10:00am PDT

Member Day Session: CHERI 101 and Standardization Session - Tariq Kurd, Codasip

Monday October 21, 2024 10:00am - 10:25am PDT

Grand Ballroom H (Level 1)

This talk covers the basics of CHERI to give a solid understanding of the technology. It covers the impact on the design of the CPU as well as how it is actually used to give memory safety, control flow integrity etc. and covers the progress with the standardization.

Speakers

Tariq Kurd

Distinguished Engineer and Lead IP Architect, Codasip

I have been chair of RISC-V code-size, and Zfinx, and these days am heavily involved in CHERI standardisation for RISC-V.

Monday October 21, 2024 10:00am - 10:25am PDT
Grand Ballroom H (Level 1)

Member Day

11:00am PDT

Member Day Session: Verifying a CPU with Sail - Tim Hutt, Codasip

Monday October 21, 2024 11:00am - 11:25am PDT

Grand Ballroom H (Level 1)

How Codasip verified a configurable CPU using the open source RISC-V Sail model.

Speakers

Tim Hutt

Senior Verification Engineer, Codasip

I'm originally a mechanical engineer (I used to work on hair dryers for Dyson!) but via a meandering path found myself in the RISC-V verification world 18 months ago. I have worked on verifying Codasip's A730 chip, including setting up our integration with the Sail model and upstreaming... Read More →

Monday October 21, 2024 11:00am - 11:25am PDT
Grand Ballroom H (Level 1)

Member Day

11:30am PDT

Member Day Session: The Need for a Packed-SIMD Extension - Rich Fuhler, Andes Technology

Monday October 21, 2024 11:30am - 11:55am PDT

Grand Ballroom H (Level 1)

The Packed-SIMD specification (P spec) is critical and integral in expanding the RISC-V ecosystem in the MCU domain and will further the development of higher value applications needing cost-efficient processing of small data parallelism for audio, voice, sound, small images, slow video, tinyML, consumer electronics, and more.

Processors which support DSP functionality are usually used to measure, filter, or compress continuous real-world analog signals. Although many DSP algorithms can be executed on a general-purpose CPU, there will be an unacceptable loss in performance for these time-critical applications. One could use the RISC-V vector extension to greatly improve performance of these algorithms, but the vector unit is typically an order of magnitude larger than a processor which implements the P specification.

This presentation will provide an overview of the specification, benchmarking numbers, development tools, and task group status.

Speakers

Rich Fuhler

Technical Director, Andes Technology

Monday October 21, 2024 11:30am - 11:55am PDT
Grand Ballroom H (Level 1)

Member Day

12:00pm PDT

Member Day Session: Sailing Toward a Single Source of Truth - Paul Clarke, Ventana Micro Systems & Derek Hower, Qualcomm

Monday October 21, 2024 12:00pm - 12:25pm PDT

Grand Ballroom H (Level 1)

Sail is a powerful language for describing a processor architecture and is already used to define a number of widely-used architectures like Arm, x86, and RISC-V.

For a Sail representation to serve as a “single source of truth” for an ISA, though, there are some unmet requirements, including comprehensive human-readable ISA documentation, as this must currently be created and maintained separately.

In addition, to make good use of Sail, some sort of transformation is required, as there are no meaningful projects that directly consume Sail. The only parser for Sail is written in OCaml. Both languages are arguably obscure enough that they present barriers to effective utilization of the RISC-V Sail specification to its full potential.

This presentation outlines alternative approaches to providing a single source of truth for the RISC-V ISA that meets the criteria of: simple format, easily parsed by both machine and human, reasonably comprehensive including providing human-readable documentation, and does not necessarily preclude the use of Sail, in which the RISC-V ecosystem has significantly invested.

Speakers

Derek Hower

Sr. Staff Engineer, Qualcomm

Derek Hower is an experienced engineer working at Qualcomm with previous stops at AMD and Intel. Derek has over a decade experience in performance modeling, including the development of several simulator infrastructures both as a manager and individual contributor. He was also the... Read More →

Paul Clarke

Software Engineer, Ventana Micro Systems

Linux user since 1.2, software developer (C, Python, OCaml, Javascript, Carbon/React, assembly, RISC-V, Power, x86, Linux, glibc, GCC, performance, porting, tuning, real-time, IPC, AIX, VM, MVS, 3D graphics, IPC), glibc and GCC maintainer, consultant, technical writer and editor... Read More →

Monday October 21, 2024 12:00pm - 12:25pm PDT
Grand Ballroom H (Level 1)

Member Day

1:30pm PDT

Marketing & Events Committee Meeting

Monday October 21, 2024 1:30pm - 2:25pm PDT

Grand Ballroom H (Level 1)

Monday October 21, 2024 1:30pm - 2:25pm PDT
Grand Ballroom H (Level 1)

Member Day

2:30pm PDT

Member Day Session: Update on Unified Discovery - Siqi Zhao, Alibaba Inc.

Monday October 21, 2024 2:30pm - 2:55pm PDT

Grand Ballroom H (Level 1)

This would be an update of the work done in the Unified Discovery TG. Unified Discovery TG is tasked to define a schema format intended for allowing the software to easily decide which ISA extension is present on the platform. This session shows the schema and related PoC.

Speakers

Siqi Zhao

Technology Expert, Alibaba DAMO Academy

Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community. He is currently serving... Read More →

Monday October 21, 2024 2:30pm - 2:55pm PDT
Grand Ballroom H (Level 1)

Member Day

3:00pm PDT

Member Day Session: Why Do We Need Yocto Project on RISC-V - Challenges and Best Practices - Khem Raj, Comcast

Monday October 21, 2024 3:00pm - 3:25pm PDT

Grand Ballroom H (Level 1)

Yocto project is a widely adopted standard set of tools and infrastructure for building Embedded systems,
ranging from complex systems based on Linux to RTOS and bare-metal applications.
It's based on OpenEmbedded build technology which has supported RISC-V the architecture from its early days.

The Yocto project has a layered architecture, which provides a scalable mechanism for adding and
customizing new hardware and software support. However, there is a balance required for the best outcome. Core architecture support in the Core layer provides common policies for RISC-V. The architecture layer (meta-riscv) adds additional RISC-V specific customizations and holds support for many SBCs with RISC-V processors.

The Yocto Project has gathered years of experience in deploying into a wide range of products e.g. cars, streaming devices, routers, and cameras to name a few. It is important to leverage these learnings and benefits for the RISC-V ecosystem. This presentation will address the challenges and gaps we have for RISC-V to become tier 1 supported architecture.

In this talk we will provide an overview of how RISC-V is supported in the Yocto project and adjacent layers. Additionally, we will describe the huge opportunity to get RISC-V supported as core architecture. RISC-V is a fast developing architecture. An important aspect of this presentation will be how to get involved in OSS development on RISC-V.

Speakers

Khem Raj

Fellow, Comcast

Khem Raj is a Linux architect at Comcast, helping several open source initiatives within the company: He is guiding the company's adoption of open source software, and becoming an active contributor to the open source components used in the RDK settop software stack. One of the most... Read More →

Monday October 21, 2024 3:00pm - 3:25pm PDT
Grand Ballroom H (Level 1)

Member Day

3:30pm PDT

Member Day Session: A Simple Plan: An API and ABI for Managing Multiple Distinct Sets of Custom Extensions - Guy Lemieux, University of British Columbia

Monday October 21, 2024 3:30pm - 3:55pm PDT

Grand Ballroom H (Level 1)

The RISC-V custom instruction encoding space provides vendors a rich opportunity to innovate. Now, the pending Composable Extensions (CX) Task Group is planning to develop ISA and non-ISA specifications to avoid collisions in opcodes and provide uniform naming, discovery, error handling, context management, and other features that will enable vendors to create a marketplace for composition and reuse of their independently authored custom (instruction) extensions and their software libraries. Instruction set switching is a way to manage this problem. A critical missing piece of the puzzle is the end user perspective: what is the application API, how will the OS manage requests, and what are the implications on the ABI? This presentation outlines a simple plan to address these issues through an API that allows users to allocate and virtualize state context in a uniform manner. We will also discuss the presently manually enforced ABI that keeps the active selector correct at all times while providing backwards compatibility with legacy custom instructions.

Speakers

Guy Lemieux

Professor, University of British Columbia

Guy is a Professor in Computer Engineering at the University of British Columbia where he teaches digital design and computer systems/architecture courses. His research focuses on improving FPGA devices and CAD tools, in particular making them easier to use and more efficient for... Read More →

Monday October 21, 2024 3:30pm - 3:55pm PDT
Grand Ballroom H (Level 1)

Member Day

4:00pm PDT

Member Day Session: High Assurance Cryptography ISE - G. Richard Newell, Microchip Technology Inc.

Monday October 21, 2024 4:00pm - 4:25pm PDT

Grand Ballroom H (Level 1)

During this session the attendees will learn about the goals, proposals, and status of the High Assurance Cryptography (HAC) Instruction Set Extension (ISE) for RISC-V vector CPUs. While overlapping the functionality of the ratified vector cryptography extensions somewhat, the HAC extensions will provide for better key management – including key encryption – and the possibility for microarchitectures to implement countermeasures against side-channel analysis, thus enabling the HAC instructions to provide secure cryptography in more use cases than the existing instructions. For example, when an adversary can gain close enough physical proximity to the CPU to monitor its electromagnetic emanations during operation, side-channel countermeasures are necessary for secure cryptographic implementations.

What may be of extra interest is that Barry Spinney, an active HAC task group member, is designing a proof-of-concept design of the core cryptographic functional unit, including the optional side-channel countermeasures, and intends to make it fully publicly available as open-source code. This talk will introduce Barry’s design to the audience.

Speakers

G. Richard Newell

Associate Technical Fellow, Microchip Technology

Richard Newell is responsible for architecting the security features for Microchip's current and future generations of FPGAs and SoC FPGAs. Richard has an electrical engineering background with over 45 years of experience in analog and digital signal processing, cryptography, control... Read More →

Monday October 21, 2024 4:00pm - 4:25pm PDT
Grand Ballroom H (Level 1)

Member Day

11:30am PDT

RISC-V Needs More Secure “Wheels”! A Perspective for/from Automotive Industry - Thomas Roecker, Infineon Technologies & Sandro Pinto, OSYX Technologies

Tuesday October 22, 2024 11:30am - 11:48am PDT

Grand Ballroom H (Level 1)

The automotive industry is experiencing a massive paradigm shift. Cars are becoming increasingly autonomous, connected, and computerized. Modern E/E-architectures are pushing for an unforeseen functionality integration density, resulting in physically separate ECUs becoming virtualized and mapped to logical partitions within a single physical MCU. While functional safety has been pivotal for vehicle certification for decades, this increasing connectivity have shed light on the need for (cyber-)security and paved the way for the release of the new standard ISO21434. RISC-V has a pivotal opportunity to transform automotive computing systems, but we argue that current ISA / extensions are not ready yet. This talk provides our critical perspective on the existing limitations, particularly the upcoming WorldGuard technology, to address virtualized MCU requirements per foreseen automotive applications. We then present our proposal to address such limitations, mainly targeting master-side protection. We complete the talk by explaining the roadmap towards a full open-source Proof-of-Concept, which includes extending QEMU, an open-source RISC-V Core, and building a complete software stack.

Speakers

Thomas Roecker

Architect Automotive, Infineon Technologies

Thomas Roecker is HW/SW-architect in Automotive division of Infineon Technologies. He holds a Dr. rer. nat. in Theoretical Physics and has a background in numerical methods and computation. Thomas is focusing on HW/SW Co-Engineering in the field of dependable systems and driving introduction... Read More →

Sandro Pinto

Co-Founder, OSYX Technologies

Sandro Pinto is co-founder of OSYX Technologies. He is also Associate Research Professor at the UMinho, Portugal. Sandro has a deep academic background and several years of industry collaboration focusing on operating systems, virtualization, and security for embedded and IoT systems... Read More →

Tuesday October 22, 2024 11:30am - 11:48am PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

11:50am PDT

Exploring Real-Time Operating System Execution Strategies on Virtual Machines in RISC-V Architecture - Ryosuke Yamamoto, Mitsubishi Electric Corporation

Tuesday October 22, 2024 11:50am - 12:08pm PDT

Grand Ballroom H (Level 1)

In embedded system development, several technical issues need to be solved to facilitate the transition from another architecture to RISC-V. For example, in existing embedded devices, there are products with multiple OSs, including RTOS. In such products, hardware virtualization is used to run General Purpose OS(GPOS) and RTOS to guarantee real-time performance and use GPOS software assets. However, some OSs (especially RTOS) are not intended to run on virtual machines. Therefore, we are researching a mechanism that enables all RTOSs to run even on a RISC-V virtual machine. In this talk, we will provide strategies for running the RTOS on virtual machines and the issues to be solved for its practical use.

Speakers

Ryosuke Yamamoto

Researcher, Mitsubishi Electric Corporation

Ryosuke Yamamoto is a researcher working at Mitsubishi Electric's Information Technology R&D Center. He has been researching system software such as OS and hypervisor for about 6 years. Recently, he has been interested in RISC-V architecture and developing a hypervisor for RISC-V... Read More →

Tuesday October 22, 2024 11:50am - 12:08pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

12:10pm PDT

Automotive Solution Empowered by RISC-V Based Security and Functional Safety Module - Jianying Peng, Nuclei System Technology

Tuesday October 22, 2024 12:10pm - 12:28pm PDT

Grand Ballroom H (Level 1)

In last year’s North America Summit, Dr. Jianying Peng presented Nuclei’s NA900 (automotive) RISC-V core as the world’s 1st ASIL-D product certified RISC-V core in the automotive session. For the past 1 year, Nuclei has continued to develop functional safety solution including world’s 2nd ASIL-D product certified RISC-V core NA300 and bus fabric with safety features. Nuclei has extended the scope to information security as well. Beyond RISC-V core and bus fabric, Nuclei has released HSM (hardware security module) based on RISC-V core recently. By doing this, the position of RISC-V in the automotive ecosystem has been further strengthened with a comprehensive set of combined RISC-V based security & functional safety solutions. Thus this year we would like to share 4 topics from technical, ecosystem and business perspectives: 1. Nuclei’s experience in functional safety and security design 2. Nuclei’s experience in automotive SoC design 3. Automotive electronics software ecosystem 4. Customer success stories and open concern of RISC-V from different customers we see in the past 2 years.

Speakers

Jianying Peng

Co-founder and CEO, Nuclei System Technology

Dr Jianying Peng, graduated from School of Micro-Nano Electronics, Zhejiang University, has more than 15 years of CPU processor design and management experience. Previously Dr Peng worked in Marvell and Synopsys where she led multiple high performance processor designs in ARM and... Read More →

Tuesday October 22, 2024 12:10pm - 12:28pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

1:55pm PDT

CPU Security in the Context of RISC-V - Sylvain Guilley, Secure-IC

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Grand Ballroom H (Level 1)

Ensuring security in Central Processing Units (CPUs) has become a critical concern. This presentation examines the importance of CPU security in the context of RISC-V , with a focus on addressing potential vulnerabilities through various security measures. In the presentation we explore and analyze different types of cyber-attacks relevant to RISC-V CPUs, such as code injection, buffer overflows and jump-orienting programming but also cyber-physical attacks like side-channel attacks, fault injections, and supply chain attacks such as hardware Trojans. We discuss the concept of Lockstep as a redundancy technique and Code & Control-Flow Integrity verification (CCFI) to enhance security and safety by detecting and correcting errors or malicious manipulations. Additionally, the presentation emphasizes the significance of industry-standard certifications (Common Criteria, FIPS 140-3) in verifying the effectiveness of security solutions. Finally, we explain why, by understanding and implementing robust security measures, RISC-V CPUs can establish a strong foundation for secure computing environments, safeguarding against diverse cyber threats and risks.

Speakers

Sylvain Guilley

Co-Founder and CTO, Secure-IC

Sylvain Guilley is co-founder and CTO at Secure-IC. Sylvain is also professor at Télécom Paris (Institut Polytechnique de Paris), associate research at the École Normale Supérieure (ENS), and adjunct professor at the Chinese Academy of Sciences (CAS). His research interests include... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Advanced

2:15pm PDT

An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications - Jamie Kim, Samsung Electronics

Tuesday October 22, 2024 2:15pm - 2:33pm PDT

Grand Ballroom H (Level 1)

I would like to introduce our success story of adopting RISC-V CPU in the embedded domain with the ability to customize the architecture. For this success, we developed a scalable, orthogonal and transparent interrupt architecture which enabled the control of extremely timing-critical tasks. I believe this architecture can be widely adopted across multiple domains with the configurability to adopt to their own requirements.

Speakers

Jamie Kim

Principal Engineer, Samsung Electronics

Jamie Kim received Ph.D. degree on Computer Architecture back in 2015 and has been working in System LSI, Samsung ever since. He led multiple MCU projects using RISC-V, which successfully went to mass production, including the first ever RISC-V based product in Samsung. Currently... Read More →

Tuesday October 22, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

2:35pm PDT

Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android - Lev Rumyantsev & Jeremiah Griffin, Google

Tuesday October 22, 2024 2:35pm - 2:53pm PDT

Grand Ballroom H (Level 1)

Berberis is an open source userspace dynamic binary translator facilitating cross-architecture development and testing of RISC-V Android applications. It translates native riscv64 code inside of an Android APK to x86_64 at runtime, enabling developers to test RISC-V builds of their apps on their workstations when target device hardware is unavailable. This presentation will cover the motivation and benefits of userspace translation versus whole-system emulation, the challenges of translating RISC-V code to x86_64, and use cases and future directions for the project.

Speakers

Jeremiah Griffin

Staff Software Engineer, Google

Jeremiah joined Google in 2022 and has been a technical lead of the Berberis RISC-V-to-x86 dynamic binary translator for Android since 2023. His areas of expertise include systems programming, automated testing, embedded and automotive software, and human-machine interfaces. He has... Read More →

Lev Rumyantsev

Software Engineer, Google

Since 2014 Lev has been working at Google on various projects to enhance user experience with Android applications on Large Screen and x86 devices. His main focus has been on developing a binary-translation layer to run ARM-compiled applications on x86 devices. In 2022 Lev also started... Read More →

Tuesday October 22, 2024 2:35pm - 2:53pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

2:55pm PDT

The Future of Mission Critical Edge Compute Is RISC-V - David Levy, Microchip

Tuesday October 22, 2024 2:55pm - 3:13pm PDT

Grand Ballroom H (Level 1)

Mission Critical Edge Compute demands high-performance MPUs with time and space partitioning capabilities to enable mixed-criticality workloads. As well, the MPUs must be built with comprehensive fault-tolerance and fault-isolation capabilities. Given these requirements, A&D and Industrial systems developers worldwide are looking to RISC-V as a key enabling technology to enable their next-generation platforms. This presentation will explore: 1) Why RISC-V for Mission Critical Edge Compute: Virtualization, Vector Processing, and WorldGuard Partitioning 2) How RISC-V is set to transform space computing 3) The opportunities for RISC-V in aviation 4) Applications for RISC-V in industrial applications This presentation will conclude with how Microchip is responding and a call-to-action for what is needed from the RISC-V ecosystem to fully capitalize on this once in a generation opportunity to transform critical infrastructure.

Speakers

David Levy

Senior Technical Staff Engineer, Product Marketing, Microchip

David recently joined Microchip in October of 2023. David brings over 30 years of Semiconductor experience that spans both business and technical acumen. David's team develops 64-bit computing solutions and high-bandwidth network communication solutions.

Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

3:15pm PDT

Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension - Markku-Juhani O. Saarinen, Tampere University

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Grand Ballroom H (Level 1)

Version 1.0.0 of the RISC-V Vector Cryptography extensions specification was ratified in late 2023 and adds high-performance cryptography operations to the comprehensive list of ISA features that RISC-V officially supports. We present the first open-source implementation of the RISC-V Vector Cryptography specification, using the PULP Project's Ara vector processor as a baseline and targeting a 28nm technology node. We present the design/verification opportunities and challenges that were encountered. Furthermore, a detailed review of the implementation and benchmarking results will be included in the presentation.

Speakers

Markku-Juhani O. Saarinen

Professor of Practice, Tampere University

Markku-Juhani O. Saarinen is a Professor of Practice (työelämäprofessori) at Tampere University (Finland). A cryptographer by training and with a long international career in security engineering, Markku has co-authored many of the ratified RISC-V cryptography extensions. Currently... Read More →

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

11:30am PDT

RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos

Wednesday October 23, 2024 11:30am - 11:48am PDT

Grand Ballroom H (Level 1)

Join us to explore the RISC-V Server Ecosystem enablement discussion, a standardization effort to ensure compatibility and reliability across RISC-V server SoCs. This talk will cover key hardware capabilities, including harts, timers, PCIe root complexes, and management features, and explain how this specification simplifies OS and hypervisor support. Attendees will learn about the collaborative efforts and partnerships driving this initiative and its impact on high-performance server applications. Discover how this work will shape the future of RISC-V in server computing.specification.

Speakers

Ved Shanbhogue

Member of Technical Staff, Rivos

Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure... Read More →

Wednesday October 23, 2024 11:30am - 11:48am PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Advanced

11:50am PDT

RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc.

Wednesday October 23, 2024 11:50am - 12:08pm PDT

Grand Ballroom H (Level 1)

ACPI for RISC-V has been under development since 3 years. It has now reached the state where every thing required to fully support ACPI on RISC-V server platforms is available. This talk will provide all the details about the specification changes and software support status for below key features required on server class platforms. 1) Hardware discovery 2) Power / performance management using LPI and CPPC 3) NUMA support 4) CPU-Cache topology information 5) IOMMU support 6) Reliability, Availability and Serviceability (RAS) support 7) Quality of Service Controller support. The talk will enlighten people that RISC-V ACPI ecosystem is ready for adoption.

Speakers

Sunil V L

Software Engineer, Ventana Micro Systems Inc

Sunil is a software engineer working for Ventana Micro Systems. He has been working on ACPI specification updates required for RISC-V as well as its upstream support.

Himanshu Chauhan

Senior Staff Engineer, Ventana Micro Systems, Inc.

Himanshu Chauhan is an open-source software enthusiast with primary interest in hypervisors, Linux kernel, and high-performance computer networks. He has 19+ years of experience developing system level software and data-path for high-performance networking devices. He is part of the... Read More →

Wednesday October 23, 2024 11:50am - 12:08pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

12:10pm PDT

Ratified N-Trace Specifications - an Overview - Robert Chyla, MIPS & Jay Gamoneda, NXP

Wednesday October 23, 2024 12:10pm - 12:28pm PDT

Grand Ballroom H (Level 1)

A set of RISC-V Trace specifications developed by N-Trace TG has been recently ratified. It consists of three separated, but interconnected specifications: * RISC-V N-Trace (Nexus based) Trace Specification * RISC-V Trace Control Specification * RISC-V Trace Connectors Specification This session will explain key trace concepts and solutions. Relations to different existing trace standards will be highlighted. Practical use-cases, implementation hints and difficulties will be elaborated. Future development and possible enhancements will be mentioned.

Speakers

Jay Gamoneda,

Front-End SoC Design Engineer, NXP

Nexus Trace encoders for RISC-V cores.SoC architecture including debug trace components.

Robert Chyla

Senior Staff Engineer (Debug and Trace), MIPS

My early engagement (Poland) included parallel programming. Later high-end computer graphics (Japan) with performance focus. In 1996 engaged with a embedded debug & trace probe vendor (California) and as VP of R&D I designed trace probes and tools. At the first RISC-V Summit I felt... Read More →

Wednesday October 23, 2024 12:10pm - 12:28pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Any

1:55pm PDT

RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built - David Chen, Stream Computing

Wednesday October 23, 2024 1:55pm - 2:13pm PDT

Grand Ballroom H (Level 1)

In this talk, we will introduce the latest work we've done on matrix extension instructions (AME), the AI software stack for the first mass production RISC-V NPU card based on matrix, and the real commercial application cases in one 1000P computing center using large models. 1. As one of the first companies in the world to submit matrix extension proposals to the Foundation, we gained a lot of implementation experience on our first mass production NPU card STCP920, would like to share with audience about how we design and use some of instructions, as well as recent works in AME. 2. Based on STCP920, we completed a full software stack for AI application, will discuss some challages we encountered on LLVM, AI compiler and operators for example. 3. We just made a big win in one 1000P computing center project using NPU card, would like to share how to use RISC-V AI accelerator to build it, what's the strength and opportunities for RISC-V, what's the senario and application for AI. Generally speaking, we believe to provide computing power means to provide service.

Speakers

David Chen

Executive Vice President, Stream Computing

David Chen, Executive Vice President of Stream Computing, responsible for RISC-V AI technology standards, international business, and ecosystem. He is currently a member of the RISC-V International TSC, Vice Chair of the Software Applications and Tools HC, and Vice Chair of the AI/ML... Read More →

Wednesday October 23, 2024 1:55pm - 2:13pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Any

2:15pm PDT

RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems

Wednesday October 23, 2024 2:15pm - 2:33pm PDT

Grand Ballroom H (Level 1)

The recently ratified RERI specification provides a open and standardized register interface specification for error reporting for RISC-V based designs targeting segments from HPC to embedded.

Speakers

Greg Favor

CTO, Ventana Micro Systems

Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing... Read More →

Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

2:35pm PDT

Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers

Wednesday October 23, 2024 2:35pm - 2:53pm PDT

Grand Ballroom H (Level 1)

This session provides an in-depth overview of a highly parameterizable open-source IOMMU IP compliant with the RISC-V IOMMU Specification v1.0. The IP was developed by Zero-Day Labs and is currently being verified in collaborative efforts with 10xEngineers. The presentation covers the implementation details of the IP, which includes features like two-stage address translation, MSI translation support, and internal IO Address Translation Caches (IOATCs) for improved performance. We discuss the verification process carried out in collaboration with 10xEngineers, which has achieved 85% of coverage targets and addressed several RTL bugs and design issues. Additionally, the session highlights the current applications of this IP in projects such as the AlSaqr 2.0 platform for autonomous nano-UAVs and the PULP Carfield architecture. The session concludes with future work plans (e.g., completing the verification and performing design optimizations) and opportunities for community collaboration to enhance the IP further.

Speakers

Saad Waheed

Manager/ Sr. Verification Engineer, 10xEngineers

Saad Waheed is a Sr. Verification Engineer and Manager at 10xEngineers. His expertise lies in the domain of design verification of RISC-V based processors and SoCs. His prior experience includes working with SiFive on the verification of its RISC-V cores for the Core IP 21G1 release... Read More →

Manuel Rodriguez

PhD Student / Hardware Architect, Zero-Day Labs

Manuel Rodríguez earned his M.Sc. degree in Electronic and Computer Engineering from the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. at the same institution. Additionally, he works as a hardware architect... Read More →

Wednesday October 23, 2024 2:35pm - 2:53pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

2:55pm PDT

Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive - Vasanth Waran, MIPS

Wednesday October 23, 2024 2:55pm - 3:13pm PDT

Grand Ballroom H (Level 1)

This session covers how simultaneous multithreading (SMT) with RISC-V Hardware threads (harts) increases the throughput efficiency of a processing subsystem for automotive applications.

Speakers

Vasanth Waran

Head of Automotive Business Unit, MIPS

Vasanth Waran heads the Automotive Business unit at MIPS. He has 22 years of experience in the Semiconductor industry and spend a majority of his career at Intel Corporation and Qualcomm Inc, in various roles from Design Engineering, Product development, Platform Applications and... Read More →

Wednesday October 23, 2024 2:55pm - 3:13pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Beginner