RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
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10:50am PDT

Demo: XuanTie RISC-V Hardware and Software Full-stack Technology - James Shi, Alibaba DAMO Academy

Tuesday October 22, 2024 10:50am - 11:10am PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this presentation, we will share the latest progress in the XuanTie IP products and software stack. We invite you join to discuss the latest developments in RISC-V.

Speakers

James Shi

Alibaba DAMO Technology Co., Ltd.

I am James Shi. I am currently a principal STE at Alibaba Damo academy, my current main focusing is on kernel & Linux OS testing for Xuantie RISC-V processors.Some of my work is also related wtih validating CPU memory models, system integration testing and performance testing for... Read More →

Tuesday October 22, 2024 10:50am - 11:10am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

11:15am PDT

Demo: Enabling Automotive Safety with Andes RISC-V IP - Marc Evans, Andes Technology

Tuesday October 22, 2024 11:15am - 11:25am PDT

Expo Hall - Exhibit Hall A - Demo Theater

Vehicles are rapidly evolving to become electrified, connected, more software-defined, and increasingly autonomous. This transformation presents a significant opportunity for open-standard RISC-V processors in automotive electronic systems, offering tailored optimization for various applications, from sensor processing and ECUs to domain, zonal, and central compute units. As the complexity of these systems continues to grow exponentially, it is crucial that the solutions adhere to rigorous standards like ISO 26262. This talk will explore these essential standards and showcase how Andes' cutting-edge solutions are designed to meet the highest levels of safety in the automotive industry.

Speakers

Marc Evans

Director of Business Development & Marketing, Andes Technology

Marc Evans recently joined Andes Technology USA as the Director of Business Development & Marketing. He has over twenty years of experience in the use of CPU, DSP, and Specialized IP in SoCs from his prior positions at Lattice Semiconductor (SoC Product Planning), Ceva (Sales and... Read More →

Tuesday October 22, 2024 11:15am - 11:25am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

12:45pm PDT

Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks - Carl Shaw, Codasip

Tuesday October 22, 2024 12:45pm - 12:55pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

CHERI is a fine-grained memory protection technology that protects your system against buffer overflows and other memory safety issues. CHERI is implemented in hardware and enabled by supporting software. This demo simulates a real buffer overflow attack on an application running a full OS. We will show how a Codasip application core with CHERI enabled can identify the attack and stop the system without any secrets being accessed.

Speakers

Carl Shaw

Safety and Security Manager, Codasip

Prior to joining Codasip, Carl has provided security engineering and architecture consultancy to leading global electronics and semiconductor companies for more than 15 years. With a Physics Ph.D., and a career mixing electronics design in government defense, and OS and firmware development... Read More →

Tuesday October 22, 2024 12:45pm - 12:55pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

12:55pm PDT

Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine - Rejeesh Shaji Babu, Ashling

Tuesday October 22, 2024 12:55pm - 1:05pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this presentation, we will provide an overview of Ashling’s TraceLLM which offers unprecedented insights into your program’s real-time behavior through an intelligent trace capture and AI LLM based analysis software engine which can be queried using a natural language, prompt-based interface. TraceLLM, which works with the Ashling Vitra-XS hardware trace probe and RiscFree software debugger has the capability to understand the entire program execution flow and can answer any questions related to the program execution in a natural language and provide quick and accurate responses, substantially bringing down the time spent by developers for debugging. Dive into your program's behavior and watch as the intelligent engine examines the captured trace and delivers unprecedented insights including pinpointing potential bottlenecks, performance issues and offering actionable insights. Enhance efficiency, accelerate problem solving, and harness the full potential of your RISC-V systems with Ashling’s TraceLLM today.

Speakers

Rejeesh Shaji Babu

VP of Engineering, Ashling

Rejeesh Shaji babu is Ashling’s VP of Engineering with a BTech in Electronics and over sixteen years’ experience in Real-time Embedded Systems with a particular emphasis on Embedded Development Tools and Debugging.

Tuesday October 22, 2024 12:55pm - 1:05pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

1:05pm PDT

Demo: More Than Point Tools: RISC-V Solutions - Larry Lapides, Synopsys

Tuesday October 22, 2024 1:05pm - 1:15pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

As RISC-V adoption grows, how are EDA tools and IP adapting to address new and evolving design challenges? From architecture exploration to design implementation and software development, SoC designers are looking for ways to take advantage of the RISC-V ecosystem and deliver optimized products with fast time-to-market. At Synopsys, we’re building RISC-V solutions to help customers from the beginning of the project to delivery and deployment, supporting the full RISC-V ISA plus custom instructions while enabling architecting of workload-optimized processors, comprehensive processor verification, and pre-silicon software development. Whether you are building your own RISC-V core, using a partner’s core, or implementing Synopsys ARC-V processor IP, Synopsys can help you meet your project requirements. This presentation will provide an overview of the broad range of Synopsys RISC-V solutions that have been proven by our customers taking RISC-V SoCs to silicon.

Speakers

Larry Lapides

Sr. Dir. Product Management, Synopsys

Larry Lapides is the Executive Director of Business Development at Synopsys, responsible for ImperasDV RISC-V processor verification products. He came to Synopsys through the acquisition of Imperas, where he was a founding member and VP Worldwide Sales and Marketing. Larry has also... Read More →

Tuesday October 22, 2024 1:05pm - 1:15pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

3:40pm PDT

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics

Tuesday October 22, 2024 3:40pm - 3:50pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this talk we will cover the latest developments in running modern transformers , such as LLama-2, on Semidynamics RISC-V "All-In-One" solution, comprising a core, a Vector Unit and a Tensor Unit. In this talk you'll learn about how ONNX RT is used to deploy modern models on Semidynamics solution, on how the ratio of the vector to tensor compute is important for balanced execution and how the all-in-one can be scaled-out to reach different performance
levels.

Speakers

Roger Espasa

CEO & Founder, Semidynamics

Roger Espasa is the founder and CEO of Semidynamics, a European IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected... Read More →

Tuesday October 22, 2024 3:40pm - 3:50pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

3:50pm PDT

Demo: Super-optimized Ubuntu and Open Source on RISC-V - Gordan Markuš, Canonical

Tuesday October 22, 2024 3:50pm - 4:00pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this session, Canonical will introduce the work being done by the organization to optimize Ubuntu, the most popular Linux operating system, for RISC-V. We will present the Canonical roadmap and vision for Ubuntu on RISC-V, this will include:

Ubuntu and Canonical roadmap for RISC-V profiles
How to enable vendor differentiation and make the unique vendor IP shine in Ubuntu
We will present the depth of our partnerships and contributions towards open source and community projects via RISC-V International and RISE

Speakers

Gordan Markuš

Director, Silicon Alliances, Canonical

With more than a decade in engineering, business development, and leadership roles working with open source software, Gordan is a leader in Canonical's Silicon Alliances organization, developing strategic relationships with the RISC-V ecosystem and various other semiconductor companies... Read More →

Tuesday October 22, 2024 3:50pm - 4:00pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

4:00pm PDT

Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V - Kelvin Low, Samsung Foundry

Tuesday October 22, 2024 4:00pm - 4:10pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In an era defined by rapid technological advancement, the intersection of semiconductor process innovation and artificial intelligence is reshaping industries and driving new paradigms of computing. This talk explores the key market trends, growth forecast and factors driving new use cases. We will also share how Samsung Foundry is enabling customer innovations in particular around RISC-V where chip and chiplet performance optimization resulting in smarter and more efficient systems. By examining current trends and future prospects, we aim to illuminate the path forward for engineers, developers, and decision-makers in harnessing the power of silicon technologies, advanced packaging, RISC-V and AI to create cutting-edge solutions that meet the demands of a rapidly evolving digital landscape.

Speakers

Kelvin Low

Vice President, Market Intelligence, Marketing & Partnerships, Business Strategy and Business Development, Samsung Foundry

Kelvin Low serves as the Vice President of Samsung Foundry Market Intelligence, Marketing &Partnerships, Business Strategy and Business Development teams. Prior to rejoining SamsungSemiconductor, he was the CEO and General Manager for SEMIFIVE US Inc and held otherTechnology, Marketing... Read More →

Tuesday October 22, 2024 4:00pm - 4:10pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

10:50am PDT

Demo: Introduction to Microchip's PIC64 Product Family and Demonstration of Video Pipeline on PIC64GX - David Levy & Dr. Battu Prakash Reddy, Microchip

Wednesday October 23, 2024 10:50am - 11:10am PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this session, Microchip will introduce the PIC64 series of 64-bit microprocessors which are built to empower and enable innovation from the industrial edge to the edge of space. We will showcase a video processing demonstration on the PIC64GX MPU family using the Curiosity Kit.

Speakers

David Levy

Senior Technical Staff Engineer, Product Marketing, Microchip

David recently joined Microchip in October of 2023. David brings over 30 years of Semiconductor experience that spans both business and technical acumen. David's team develops 64-bit computing solutions and high-bandwidth network communication solutions.

Dr. Battu Prakash Reddy

Senior Manager, Design Engineering, Microchip

Associated with Microchip/Microsemi since December 2013, Prakash and his team developed various FPGA IPs and solutions for high-speed video camera, display and broadcast interfaces.

Wednesday October 23, 2024 10:50am - 11:10am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

11:10am PDT

Demo: Andes ACE: Enabling Custom RISCV Instructions Safely - Darren Jones, Andes Technology

Wednesday October 23, 2024 11:10am - 11:20am PDT

Expo Hall - Exhibit Hall A - Demo Theater

One promise of RISC-V is that it enables Architects, Systems Designers, and SW Developers to add custom instructions. However, if you don’t have your own CPU design team, how do you do this without breaking the RISC-V standard part of the pipeline? This talk will describe how the Andes Custom Extensions (ACE) enables simple and safe insertion of custom instructions while enabling software development and performance modeling.

Speakers

Darren Jones

Solution Architect, Andes Technology

Darren started his career designing MIPS processors. From there, he transitioned to building large SOC’s utilizing ARM processor IP. More recently, he was VP of VLSI at two RISC-V startups building huge SOC’s for machine learning and AI. He is now a Solution Architect at Andes... Read More →

Wednesday October 23, 2024 11:10am - 11:20am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

about Darren started his career designing MIPS processors. From there, he transitioned to building large SOC’s utilizing ARM processor IP. More recently, he was VP of VLSI at two RISC-V startups building huge SOC’s for machine learning and AI. He is now a Solution Architect at Andes Technology leveraging his CPU and SOC experience to help systems designers solve their unique problems using innovative IP.

12:45pm PDT

Demo: Accelerate RISC-V Development with Tessent UltraSight-V - Francisca Tan, Siemens EDA

Wednesday October 23, 2024 12:45pm - 12:55pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this presentation, we will unveil Tessent UltraSight-V, an end-to-end solution consisting of embedded IP and software designed to provide comprehensive, efficient debugging and trace capabilities that integrates with industry standard tool to further empower embedded software engineers in developing high-performance embedded software. The integration of Tessent UltraSight-V on-chip IP modules and host software empowers engineers to efficiently diagnose the root causes of unexpected behavior and underperformance. Utilizing effective, non-intrusive techniques such as encoded processor trace based on the Efficient Trace (E-trace) standard, logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads, this solution minimizes debugging delays and accelerates your SoC projects, ensuring they meet their market deadlines.

Speakers

Francisca Tan

Technical Program Manager, Siemens EDA

Dr. Francisca Tan is the Technical Program Manager for Tessent Embedded Analytics at Siemens EDA. With nearly a decade of experience in the semiconductor industry, she has held various engineering, research, and management roles at Siemens, Arm, and Intel. Her interest encompasses... Read More →

Wednesday October 23, 2024 12:45pm - 12:55pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

12:55pm PDT

Demo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips - Dennis Griffith, Lauterbach

Wednesday October 23, 2024 12:55pm - 1:05pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

RISC-V cores can be found in more and more chips - as the main CPU(s) or as a companion core together with other CPU architectures. They can be implemented in subarchitectures like RISC-V RV32/RV64, AndesCore™ V5 or SiFive® Core IP. While the complexity of SoCs grows with the number of cores and the number of different core (sub)architectures, the challenges for embedded developers grow even more with operating systems, hypervisors, and other software running on multiple cores.

In this presentation, Lauterbach, market leader for development tools and strategic member of the RISC-V foundation, show how developers can overcome these challenges with the right tools and debug strategies. They explain how to debug cores from RISC-V and other architectures simultaneously via one debug interface and one debug probe to gain insight into the entire embedded system. The presentation covers real-time on- and off-chip tracing for all major RISC-V trace systems as well as the utilization of standardized RISC-V debug and trace interfaces.

Through this presentation the attendee learns that multicore debugging with RISC-V cores is not rocket science and that there are efficient methods to master even complex chips with complex software configurations.

Speakers

Dennis Griffith

Senior Field Applications Engineer, Lauterbach

Dennis Griffith is a Senior Field Applications Engineer at Lauterbach specializing in debugging software, hardware, and validating debugger access for complex System-on-Chip (SoC) designs. He holds a BSEE from the University of Portland and has over 20 years of experience. Dennis's... Read More →

Wednesday October 23, 2024 12:55pm - 1:05pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

2:00pm PDT

Hackathon Presentations

Wednesday October 23, 2024 2:00pm - 3:00pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

Participants from Monday's hackathon present their solution in the Expo Hall on the Demo Theater. Winner takes home a big prize!

Wednesday October 23, 2024 2:00pm - 3:00pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Onsite Activities

3:20pm PDT

Akeana : Breaking Performance Barriers - Graham Wilson, Akeana

Wednesday October 23, 2024 3:20pm - 3:30pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

This is a presentation introducing the RISC-V Processor IP company, which has recently come out of stealth mode. The presentation will go through the company, range of IP products available and benefits offered to customers.

Speakers

Graham Wilson

Head of Product, Akena

Graham has over 25 years of experience in the semiconductor, IP industry with 15 years in processor IP, working at companies as Tensilica/Cadence, Synopsys and SiFive. His main area of focus has been DSP, Vector processors, with recent focus on AI computation processors. At Akeana... Read More →

Wednesday October 23, 2024 3:20pm - 3:30pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

3:30pm PDT

RISC-V Opportunities in Brazil - J. E.Bertuzzo, Eldorado Institute

Wednesday October 23, 2024 3:30pm - 3:40pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

The objective would be to present the Brazilian innovation ecosystem that operates in various business segments and the impact that RISC-V technology can bring to companies operating in these segments.

Speakers

J. E.Bertuzzo

R&D Executive Director, Eldorado Institute

Graduated in Electrical Engineering from the State University of Campinas - Brazil. Has worked for 40 years on research and development projects in the areas of information technology and telecommunications. Has been at the Eldorado Institute since 2004, where he was responsible for... Read More →

Wednesday October 23, 2024 3:30pm - 3:40pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater