RISC-V Summit

Implementing and Verifying RISC-V Nexus Trace Compliant Trace Encoder for High Performance Cores - Sajosh Janarthanam, Tenstorrent Inc.
In this poster, we present the N-trace infrastructure, which supports instruction tracing for multiple out-of-order RISC-V cores. We discuss the architectural and microarchitectural decisions involved in designing the Encoder. Furthermore, we describe the infrastructure established to facilitate efficient trace transmission. Finally, we discuss the strategies employed to verify the Encoder and its associated components.

RISC-V "V" Vector Extension (RVV) with Reduced Number of Vector Registers - Eino Jacobs & Dmitry Utyanski, Synopsys
Reduce the number of vector registers to reduce the area of small processors for DSP applications.

MAMBO: Dynamic Binary Modification on RISC-V - John Kressel & Mikel Lujan, University of Manchester
Dynamic Binary Modification (DBM) is an important technique used in computer architecture simulators, virtualization, and program analysis, to name a few examples. The software ecosystem of RISC-V is maturing at pace, but is still missing a high-performance, optimized DBM. Addressing this requirement is key to improving the overall software ecosystem. This paper presents a comprehensive performance evaluation study for a DBM (MAMBO) which has been ported and optimized for 64-bit RISC-V. The main optimizations for DBM on RISC architectures have been implemented and tuned for RISC-V to address specific architectural features. For example, jump trampolines have been specifically developed to address the short direct branch range specified by the RISC-V ISA. The evaluation shows that for SPEC CPU2006 the geometric mean overhead is of 14.5%, with SPECint having the largest contribution with a geometric mean of 28.5%, while SPECfp has only an overhead of 5.6%. Concretely, this results in a reduction in runtime for h264ref from over 75 hours using the baseline DBM, to 2.2 hours with optimizations applied.

TestRIG - Professor Simon Moore, University of Cambridge
TestRIG is a framework for directed randomized testing of RISC-V cores. It leverages the QuickCheck automatic testing library and the RISC-V sail model to find potential trace divergences and report minimal instruction sequences triggering a bug in an implementation, helping with RTL bring-up and debugging.

MXM-RVV: Easy Multicore X Multithreading with Vectors via Composable Extensions + DMA - Joseph Maheshe, Guy Lemieux & Brandon Freiberger, University of British Columbia
We revisit the topic of multithreaded vector processors, but now within the RISC-V architecture. By combining data-level and thread-level parallelism, we further improve performance. We create an SoC with one hart and multiple RVV vector units, where each vector unit contains multiple contexts (multithreading), using the Draft CX Specification. We add an independent instruction queue to each context within each vector unit, thereby enabling asynchronous multicore, multithreaded execution of vector instructions with a single scalar thread and hardware scheduling of the parallel queues.
To make this work, we show that non-blocking vector loads and stores are essential to hide memory latency by executing instructions from other contexts. We use a round-robin scheduling scheme for fine-grained multithreading. We illustrate how to write software to target the MXM-RVV and show that it requires minimal changes.

Open-Source Self-Checking RISC-V Architectural Tests - Darshak Koshiya, Tenstorrent Inc.
This presentation introduces a collection of self-checking RISC-V Instruction Set Architecture (ISA) directed tests designed to help streamline the verification process for RISC-V designs. These tests leverage an end-of-test mechanism, that eliminates the need for pre-defined expected outputs and simplifies test execution. These open-source tests employ randomly generated operands and data avoiding the pitfalls of the using simple constants.This presentation will delve into the design and implementation details of these pen-source tests, showcasing their effectiveness in the verification of RISC-V ISA implementations and facilitating a more streamlined verification process for RISC-V cores. 

Emulation-Friendly, Efficient, Self-Checking  RISC-V Compliant JTAG-DFD Testbench Mechanism - Pravin Tavagad & Midhun Varman, Tenstorrent
The increasing complexity of modern electronic systems and RISC-V based SoC designs demands robust testing methodologies to ensure reliability and performance. JTAG testbenches have become essential tools for debugging and verifying integrated circuits. However, traditional JTAG testbenches often face challenges in terms of emulation friendliness, efficiency, quick turn around time, reusability and scalability. We present an approach that addresses the critical need for an advanced JTAG testbench for complex RISC-V based designs that overcomes these limitations. Additionally, our approach supports access to various RISC-V components such as the RISC-V Debug module via the RISC-V Debug Transport Module (DTM), the RISC-V compliant Trace module

Simplifying Sail and Architecture Compatibility Testing Setups with Containers - Greg Sterling, RISC-V International

RISC-V Documentation Guidelines: Is it 'Which' or 'That'? - Kersten Richter & Bill Traynor, RISC-V International

Commercializing CHERI on a Codasip A730 RISC-V Application Core - Tariq Kurd, Codasip
Memory safety continues to cause widespread and costly cyber security problems. Data breaches often arise from memory safety vulnerabilities leading to multi-million dollar losses for victims; for example, losses due to the well-known OpenSSL Heartbleed bug are estimated to exceed $500 million. Therefore, there is increasing interest in the Capability Hardware Enhanced RISC Instructions (CHERI) which is an ISA extension that mitigates memory safety vulnerabilities by design. CHERI has been primarily a research project until now! The University of Cambridge, which originated the technology, partnered with Codasip to propose a CHERI extension for RISC-V. Codasip also unveiled the first commercial implementation of a CHERI RISC-V: the A730 processor. In this poster, we introduce the A730 processor microarchitecture and highlight the main challenges to supporting CHERI RISC-V. We also describe the key differences between A730 implementations with and without CHERI support. In our experience, the A730 with CHERI is about 4% larger in area than an A730 without CHERI.

CHERI RISC-V Standardization - Peter Rugg, University of Cambridge
CHERI is a cross-architecture security technology, adding memory safety and compartmentalization features via capability support in the hardware. This poster will present the current effort to standardize the architectural extensions required to obtain these benefits in RISC-V: currently an effort shared by University of Cambridge, Codasip, Google, and others. The standardization work has been proceeding at pace, with a concrete specification document available, and extensive community interaction to iron out edge cases and ensure applicability to a wide range of uses.

The CHERI Alliance – Getting the Industry Together to Tackle a $10T / Year Problem - Mike Eftimakis, CHERI Alliance
Cybercrime costs the World more than $10T / year, and this amount is growing at an alarming rate. A study of software vulnerabilities has shown that over the past 20 years, memory attacks represented more than 70% of them. CHERI technology has been developed to solve the problem and has been proven to work. After 14 years of research and prototyping, CHERI is now ready to get out of the lab! A new CHERI SIG has been formed in RISC-V International, but adoption won’t happen without a significant industry-led effort: this is the goal of the CHERI Alliance.

High Performance and Efficiency 512-B & 1024-B VLEN Vector Processor and AI Related Accelerator - Nathan Ma, Nuclei System Technology
In this presentation, we delve into the powerful synergy between RISC-V Vector Processing, with a spotlight on the transformative RVV1.0 extension (specifically on VLEN=512b and 1024b), and AI acceleration. RISC-V, becomes even more impactful with the introduction of the RVV1.0 extension, specifically designed to elevate vector processing capabilities. In 2024, we released our Intelligence Class Core IP Series, specifically focus on AI applications and others require intensive parallel vector computing capability.

Enhancing RISC-V ISA to Support Sub-FP8 Quantization for Machine Learning Models -
Mengshiun Yu & Jhih-Kuan Lin, National Tsing Hua University
In this session we'll present our research proposes extending the RISC-V Instruction Set Architecture (ISA) to support sub-FP8 quantized data formats, optimizing AI and machine learning models for low-power edge devices. The study develops new instructions to enable the RISC-V CPU core to handle data types below FP8, such as 6-bit and 4-bit formats. These improvements enhance AI workload performance and energy efficiency, allowing complex machine learning tasks to be performed locally on edge devices like smartphones, IoT devices, and wearables. The proposed ISA extension supports mixed-precision workloads and ensures backward compatibility with existing hardware for easy adoption. The research includes designing a new sub-FP8 extension with computational, configuration, load/store, and conversion instructions. The design is demonstrated with two examples using assembly code: one for adding two FP8 (E5M2) values and another for performing saxpy computation with vector extension.

Towards Generative AI for RISC-V Verification - Sergei Chirkunov, Imagination Technologies
Generative AI has considerable potential in CPU verification. In this work, we adapt networks and techniques developed in the context of large language models (LLMs) for natural language processing to RISC-V assembly sequences to facilitate future applications to CPU verification. In particular, we demonstrate the ability to generate novel assembly sequences of guaranteed-valid instructions with a small, efficient language model. We anticipate that our work will ultimately facilitate a variety of verification tasks such as stimulus generation, assessment of the similarity between sequences, and identification of minimal test batteries that exercise the state space.

The Efficient Way to Design a RISC-V Edge AI Processor with Software Hardware Co-Design Methodology - Meng Zhang, Terapines Technology (Wuhan) Co., Ltd 
This talk will show you how to improve the performance of an AI model running on a virtualized RISC-V architecture with software hardware co-design methodology. This method can be done all the way from micro-architecture design, to support adding customized instructions in compiler, debugger and simulator, and to profile AI model performance on virtualized platform by one person in as short as a few hours, without knowing how to customize compiler, debugger or simulator as all of those have automatically done in the our software hardware co-design flow.

Creating Custom RISC-V Processors Using ASIP Design Tools: A Neural Network Acceleration Case Study - Gert Goossens, Synopsys
The AI revolution triggers an increased awareness for application-specific instruction-set processors (ASIPs). A RISC-V architecture can be extended with specialized datapaths, storages, and custom instructions to accelerate AI workloads. New instructions can be encoded in RISC-V's reserved opcode space or in additional parallel slots of an extended long instruction word. Notwithstanding the specialization, compatibility with and reuse of the RISC-V ecosystem is maintained.
Synopsys’ ASIP Designer tool-suite enables the design of custom RISC-V processors. Starting from a formal ISA model, it assists designers in selecting ISA extensions, generates an SDK with an optimizing compiler supporting the extensions, and produces an efficient RTL implementation.
We illustrate this approach with the design of a custom RISC-V processor to accelerate convolutional neural network algorithms for edge AI, with programming support for TensorFlow Lite for Microcontrollers (TFLM). ISA specialization includes the introduction of 4-lane SIMD with a local vector memory, 4 specialized convolution units with 16 multipliers each, dedicated accumulator registers, and 2-way instruction-level parallelism.

Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG Plugins - Matheus Ferst, Instituto de Pesquisas ELDORADO
Following the gap analysis done in the second half of 2023, the SIG-Vector has been working on specifying instructions to accelerate matrix operations. Two Task Groups were proposed to explore different approaches. The "Attached Matrix Extension" (AME) is working on a set of instructions independent of other extensions and requires new registers to hold matrix data. The Integrated Matrix Extension (IME) proposes the reuse of the Vector Registers introduced by the V extension. The AME solution is similar to how other architectures added matrix operations, like Intel's AMX and ARM's SME, while the IME proposal resembles how the POWER architecture added matrix operations. The IME might also help applications that interleave matrix and vector operations by avoiding data movement between different types of registers.
To verify how commonly that happens on AI/ML workloads, we developed a QEMU TCG Plugin to instrument the inference of eight CNN models optimized to use the IME-like POWER10 matrix instructions. The results also show some types of vector operations that interact with matrix data and would be helpful in an AME implementation to avoid sending data back to memory.

Enhancing the Future of AI/ML with Attached Matrix Extension - Jing Qui, Alibaba
We've now updated Xuantie Attached Matrix Extension ISA to keep pace with rapid advances in AI.
The new matrix ISA uses 64-bit instructions. These self-contained long instructions can support more architectural registers, facilitate sparse operations, include longer immediates and more metadata. This enhanced encoding scheme increases both the flexibility and efficiency of matrix computations. Another enhancement is the introduction of structured sparsity techniques that allow for variable sparsity ratios (N:M sparsity) across k dimensions. The new extension also supports innovative data types, such as int4/fp8, commonly used in large language models. In addition to multi-precision, it also supports mixed-precision operations. Har

Optimizing Image Signal Processing with RISC-V FPGA - Umer Imran &Bilal Zafar, 10xEngineers
In this session, we will explore the successful implementation of Infinite-ISP, a comprehensive Image Signal Processor (ISP) development platform, on an Efinix FPGA leveraging a RISC-V core. Infinite-ISP provides a full-stack solution, from algorithm development to RTL design, FPGA/ASIC implementation, and associated firmware and tools, creating a unified platform that accelerates ISP development. Our case study will delve into the technical details of integrating Infinite-ISP with a RISC-V based FPGA, highlighting the challenges faced and the innovative solutions devised to overcome them. Attendees will learn about the performance benchmarks achieved and the significant enhancements in efficiency and scalability. Additionally, we will discuss the broader implications of using an open-source RISC-V architecture in specialized applications like ISP development. Join us to discover how leveraging RISC-V for ISP development can open new possibilities in image processing technology. This presentation is ideal for engineers, developers, and decision-makers interested in the cutting-edge intersection of RISC-V and image signal processing.

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores - Tammo Mürmann & Florian Meisel, Technical University of Darmstadt
Custom instruction set architecture extensions (ISAX) are an energy-efficient and cost-effective way to accelerate modern workloads. However, exploring different combinations of base cores and ISAXes for a specific application requires automation and a level of portability across microarchitectures not provided by existing approaches.
To that end, we present an end-to-end flow for ISAX specification, generation, and integration into a number of host cores with a range of different microarchitectures. For ISAX specification, we leverage CoreDSL, an open-source C-like behavioral architecture description language. Hardware generation is handled by Longnail, a domain-specific high-level synthesis tool that compiles CoreDSL specifications into hardware modules compatible with the open-source SCAIE-V extension interface, which we use for automatic integration into the host cores.
We demonstrate our tooling by generating ISAXes using a mix of features, including complex multi-cycle computations, memory accesses, branch instructions, custom registers, and decoupled execution across five MCUs and two application-class cores, and evaluate the quality of results on a 22nm ASIC process.

RISC-V & Its Role in Silicon Lifecycle Management - Vivek Chickermane, Siemens EDA
This session will focus on the use of RISC-V processors and the RISC-V Trace specification in safety critical applications and the ability to implement embedded solutions that serve as a foundation for a comprehensive SoC Silicon debug and continuous monitoring system.

Introduction of Deploying the Rv64ilp32 ABI on the Kendryte K230d for Productization - Ren Guo, Alibaba XuanTie
Over the past year, the Alibaba XuanTie and PLCT teams have been dedicated to promoting the rv64ilp32 ABI, as it effectively addresses the need to run ILP32 software on existing RVA Profiles. Unlike before, the RISC-V 64ilp32 ABI steers clear of the Linux userspace scenario, focusing instead on underlying software such as the Linux kernel, RTOS, firmware, and hypervisors. We completed the first productized SDK based on the rv64ilp32 ABI on Canaan's k230d chip, enabling rv64ilp32 Nuttx and Linux. The k230d is Canaan Kendryte's new product, a repackaged chip based on k230 that incorporates 128MB of internal memory to reduce costs. Thus, there is a strong demand for the ILP32 ABI. This presentation will demonstrate the advantages of rv64ilp32 through actual test data on the k230d EVB: it avoids a 30% waste of memory footprint and significantly improves the performance of Linux linked list traversal. We innovated sign-extend addressing to replace the traditional zero-extend addressing. The newer XuanTie processors support a new relaxed-extend addressing mode to gain more performance. Finally, the presentation will share progress and plans for the rv64ilp32 ABI on Embedded Hypervisors.