RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
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9:00am PDT

Applications & Tools Horizontal Committee Meeting

Monday October 21, 2024 9:00am - 9:25am PDT

Grand Ballroom H (Level 1)

Monday October 21, 2024 9:00am - 9:25am PDT
Grand Ballroom H (Level 1)

Member Day

9:00am PDT

Member Day Session: Realizing RISC-V Certification, and What it Means for your Verification - Adnan Hamid, Breker Verification Systems

Monday October 21, 2024 9:00am - 9:25am PDT

Theater (Level 2)

For RISC-V to be successful, industry confidence in the quality of produced cores is critical, driving the mission of the RISC-V International Certification Steering Committee (CSC). It is recognized that a high degree of commercial-grade testing is required, leveraging tests from verification specialists, as well as existing work. The CSC has noted the need for small and large core certification, as well as the SoC components around them.

This presentation will analyze the CSC requirements and detail the types of tests that are likely be required, given the focus on architectural analysis that goes much further than basic ISA compliance. We will discuss the kind of scenarios to be validated, and how this can best be accomplished using the required self-checking content. The certification tests could also form the foundation of a comprehensive microarchitectural verification suite. While this is not the goal of certification, we will demonstrate how this might benefit overall verification.

Attendees will gain a greater understanding of the implementation of a certification flow as part of a broader verification approach, and the impact on this on their cores or SoCs.

Speakers

Adnan Hamid

President & CTO, Breker Verification Systems, Inc.

Adnan Hamid is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System... Read More →

Monday October 21, 2024 9:00am - 9:25am PDT
Theater (Level 2)

Member Day

9:30am PDT

Member Day Session: Exploring the Programming Model of the RISC-V IOPMP - Paul Ku, Andes Technology

Monday October 21, 2024 9:30am - 9:55am PDT

Grand Ballroom H (Level 1)

The specification of the IOPMP, I/O Physical Memory Protection Unit, is nearing stability, making it an opportune moment to introduce the IOPMP programming model to users. This presentation will demonstrate the bottom-up programming model of IOPMP in M-mode, H-mode, and VS/S-mode.
In M mode, we utilize a native library, libiopmp, while H/S/VS-mode employs the SBI for IOPMP with necessary security checks. Within libiopmp, we will explore how to group the regions of a specific device into a memory domain, which can be easily switched and shared. This clarifies why IOPMP prefers the per-device association programming model over ARM's per-rule association model.

The SBI, positioned above the libiopmp, allows the other modes to manipulate the IOPMP. A hypervisor should be able to allocate devices for a guest OS. IOPMP's memory domain offers a convenient method for associating devices with a specific guest OS.

In H/S mode, hot-plug devices may necessitate IOPMP updates. In VS mode, a guest OS typically lacks knowledge about the physical memory, so the IOPMP's updates are generally transparent. Software in the higher privileged modes helps to manipulate IOPMP(s) behind guest OS requests.

Speakers

Paul Ku

Deputy Technical Director, Andes Technology

Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. Besides, in the RISC-V International, he served the TEE Task Group as the vice-chair in 2021 and has been the chair of the IOPMP TG since 2022. He ever worked for Faraday Technology... Read More →

Monday October 21, 2024 9:30am - 9:55am PDT
Grand Ballroom H (Level 1)

Member Day

9:30am PDT

Member Day Session: RISC-V for HPC: Where We Currently are and Where We Need to Go - Nick Brown, University of Edinburgh

Monday October 21, 2024 9:30am - 9:55am PDT

Theater (Level 2)

The powerhouse which unlocks the ability to simulate complex, real world problems, as well as powering AI and ML workloads, High Performance Computing (HPC) is a crucial part of the modern day world. Supercomputers most commonly leverage x86 CPUs and Nvidia or AMD GPUs, however, as the ever-increasing demand by users for more capability meets a growing focus on sustainability, alternative technologies such as RISC-V are important.

RISC-V can offer benefits in performance and energy efficiency to HPC through the potential for specialisation, however the HPC community is yet to embrace RISC-V. But with increased availability of commodity RISC-V high performance CPUs (e.g. the SG2042) and PCIe accelerator cards, RISC-V is becoming a more serious option.

In the RISC-V HPC SIG our role to help drive adoption, and in this talk I will describe where the RISC-V ecosystem currently lies for HPC, explore performance and energy efficiency of latest generation RISC-V hardware against that currently more commonplace in HPC, and highlight key areas that we as the RISC-V community should prioritise to drive RISC-V adoption in HPC. Ultimately acting as a call to action for the RISC-V community.

Speakers

Nick Brown

Senior Research Fellow, EPCC at the University of Edinburgh

Dr Nick Brown is a Senior Research Fellow at EPCC, the University of Edinburgh. His main interest is in the role that novel hardware can play in future supercomputers, and is specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively... Read More →

Monday October 21, 2024 9:30am - 9:55am PDT
Theater (Level 2)

Member Day

9:30am PDT

Automotive Market Development Meeting

Monday October 21, 2024 9:30am - 10:30am PDT

206 (Level 2)

Monday October 21, 2024 9:30am - 10:30am PDT
206 (Level 2)

Member Day

10:00am PDT

Member Day Session: CHERI 101 and Standardization Session - Tariq Kurd, Codasip

Monday October 21, 2024 10:00am - 10:25am PDT

Grand Ballroom H (Level 1)

This talk covers the basics of CHERI to give a solid understanding of the technology. It covers the impact on the design of the CPU as well as how it is actually used to give memory safety, control flow integrity etc. and covers the progress with the standardization.

Speakers

Tariq Kurd

Distinguished Engineer and Lead IP Architect, Codasip

I have been chair of RISC-V code-size, and Zfinx, and these days am heavily involved in CHERI standardisation for RISC-V.

Monday October 21, 2024 10:00am - 10:25am PDT
Grand Ballroom H (Level 1)

Member Day

10:00am PDT

Member Day Session: Improving Performance Analysis on RISC-V - Beeman Strong & Atish Patra, Rivos, Inc

Monday October 21, 2024 10:00am - 10:25am PDT

Theater (Level 2)

The Performance Analysis SIG works to improve the state of performance analysis on RISC-V systems, by overseeing both the development of new ISA extensions to improve visibility, and the enabling of the software ecosystem (firmware, OS, tools). In this talk, chair Beeman Strong and member Atish Patra will recap the work completed in the last year, including 4 new ISA extensions and several improvements to Linux perf, and introduce some ongoing work. This will include progress updates on the Performance Events TG, the Performance Event Sampling TG, the Self-hosted Trace TG, and further Linux kernel/perf tool enhancements that aim to allow performance analysis on RISC-V to match or exceed the experience on competing ISAs.

Speakers

Beeman Strong

Hardware Architect, Rivos Inc.

Beeman Strong is lead architect for CPU performance monitoring, debug, and trace at Rivos Inc. Prior to that he spent 25 years working at Intel, with the last 11 working on ISA definition with a focus on performance monitoring & trace. In that role he worked closely with software... Read More →

Atish Patra

Linux kernel Engineer, Rivos

Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.

Monday October 21, 2024 10:00am - 10:25am PDT
Theater (Level 2)

Member Day

11:00am PDT

Member Day Session: Verifying a CPU with Sail - Tim Hutt, Codasip

Monday October 21, 2024 11:00am - 11:25am PDT

Grand Ballroom H (Level 1)

How Codasip verified a configurable CPU using the open source RISC-V Sail model.

Speakers

Tim Hutt

Senior Verification Engineer, Codasip

I'm originally a mechanical engineer (I used to work on hair dryers for Dyson!) but via a meandering path found myself in the RISC-V verification world 18 months ago. I have worked on verifying Codasip's A730 chip, including setting up our integration with the Sail model and upstreaming... Read More →

Monday October 21, 2024 11:00am - 11:25am PDT
Grand Ballroom H (Level 1)

Member Day

11:00am PDT

Security Horizontal Committee Update - Andrew Dellow, Qualcomm & Ravi Sahita, Rivos Inc.

Monday October 21, 2024 11:00am - 11:25am PDT

Theater (Level 2)

Speakers

Andrew Dellow

Director of Engineering, Qualcomm & Chair, RISC-V Security HC, Qualcomm

Ravi Sahita

Principal Security Architect, Rivos Inc.

Ravi Sahita is a Principal Security Architect at Rivos Inc, and vice-chair of the Security HC at RVI. He is an expert in ISA/platform virtualization, trusted execution, and exploit prevention. In past work, he led the security arch. for confidential computing on x86 servers, exploit... Read More →

Monday October 21, 2024 11:00am - 11:25am PDT
Theater (Level 2)

Member Day

11:00am PDT

AI Market Development Meeting

Monday October 21, 2024 11:00am - 12:30pm PDT

206 (Level 2)

Monday October 21, 2024 11:00am - 12:30pm PDT
206 (Level 2)

Member Day

11:30am PDT

Member Day Session: The Need for a Packed-SIMD Extension - Rich Fuhler, Andes Technology

Monday October 21, 2024 11:30am - 11:55am PDT

Grand Ballroom H (Level 1)

The Packed-SIMD specification (P spec) is critical and integral in expanding the RISC-V ecosystem in the MCU domain and will further the development of higher value applications needing cost-efficient processing of small data parallelism for audio, voice, sound, small images, slow video, tinyML, consumer electronics, and more.

Processors which support DSP functionality are usually used to measure, filter, or compress continuous real-world analog signals. Although many DSP algorithms can be executed on a general-purpose CPU, there will be an unacceptable loss in performance for these time-critical applications. One could use the RISC-V vector extension to greatly improve performance of these algorithms, but the vector unit is typically an order of magnitude larger than a processor which implements the P specification.

This presentation will provide an overview of the specification, benchmarking numbers, development tools, and task group status.

Speakers

Rich Fuhler

Technical Director, Andes Technology

Monday October 21, 2024 11:30am - 11:55am PDT
Grand Ballroom H (Level 1)

Member Day

11:30am PDT

Security Model Update - Nicholas Wood, Imagination Technologies

Monday October 21, 2024 11:30am - 11:55am PDT

Theater (Level 2)

Speakers

Nicholas Wood

Security Architect, Imagination Technologies

Monday October 21, 2024 11:30am - 11:55am PDT
Theater (Level 2)

Member Day

12:00pm PDT

Member Day Session: Sailing Toward a Single Source of Truth - Paul Clarke, Ventana Micro Systems & Derek Hower, Qualcomm

Monday October 21, 2024 12:00pm - 12:25pm PDT

Grand Ballroom H (Level 1)

Sail is a powerful language for describing a processor architecture and is already used to define a number of widely-used architectures like Arm, x86, and RISC-V.

For a Sail representation to serve as a “single source of truth” for an ISA, though, there are some unmet requirements, including comprehensive human-readable ISA documentation, as this must currently be created and maintained separately.

In addition, to make good use of Sail, some sort of transformation is required, as there are no meaningful projects that directly consume Sail. The only parser for Sail is written in OCaml. Both languages are arguably obscure enough that they present barriers to effective utilization of the RISC-V Sail specification to its full potential.

This presentation outlines alternative approaches to providing a single source of truth for the RISC-V ISA that meets the criteria of: simple format, easily parsed by both machine and human, reasonably comprehensive including providing human-readable documentation, and does not necessarily preclude the use of Sail, in which the RISC-V ecosystem has significantly invested.

Speakers

Derek Hower

Sr. Staff Engineer, Qualcomm

Derek Hower is an experienced engineer working at Qualcomm with previous stops at AMD and Intel. Derek has over a decade experience in performance modeling, including the development of several simulator infrastructures both as a manager and individual contributor. He was also the... Read More →

Paul Clarke

Software Engineer, Ventana Micro Systems

Linux user since 1.2, software developer (C, Python, OCaml, Javascript, Carbon/React, assembly, RISC-V, Power, x86, Linux, glibc, GCC, performance, porting, tuning, real-time, IPC, AIX, VM, MVS, 3D graphics, IPC), glibc and GCC maintainer, consultant, technical writer and editor... Read More →

Monday October 21, 2024 12:00pm - 12:25pm PDT
Grand Ballroom H (Level 1)

Member Day

12:00pm PDT

SOC Infrastructure Horizontal Committee Update - Ved Shanbhogue, Rivos Inc.

Monday October 21, 2024 12:00pm - 12:25pm PDT

Theater (Level 2)

Speakers

Ved Shanbhogue

Member of Technical Staff, Rivos

Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure... Read More →

Monday October 21, 2024 12:00pm - 12:25pm PDT
Theater (Level 2)

Member Day

1:30pm PDT

Unprivileged ISA Committee Update - Earl Kilian, Aril Inc.

Monday October 21, 2024 1:30pm - 1:55pm PDT

Theater (Level 2)

Speakers

Earl Kilian

CTO, Aril

Monday October 21, 2024 1:30pm - 1:55pm PDT
Theater (Level 2)

Member Day

1:30pm PDT

Marketing & Events Committee Meeting

Monday October 21, 2024 1:30pm - 2:25pm PDT

Grand Ballroom H (Level 1)

Monday October 21, 2024 1:30pm - 2:25pm PDT
Grand Ballroom H (Level 1)

Member Day

2:00pm PDT

Restarting the Automotive SIG - Andrea Gallo, RISC-V

Monday October 21, 2024 2:00pm - 2:25pm PDT

Theater (Level 2)

Speakers

Andrea Gallo

VP of Technology, RISC-V

Monday October 21, 2024 2:00pm - 2:25pm PDT
Theater (Level 2)

Member Day

2:30pm PDT

Member Day Session: Update on Unified Discovery - Siqi Zhao, Alibaba Inc.

Monday October 21, 2024 2:30pm - 2:55pm PDT

Grand Ballroom H (Level 1)

This would be an update of the work done in the Unified Discovery TG. Unified Discovery TG is tasked to define a schema format intended for allowing the software to easily decide which ISA extension is present on the platform. This session shows the schema and related PoC.

Speakers

Siqi Zhao

Technology Expert, Alibaba DAMO Academy

Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community. He is currently serving... Read More →

Monday October 21, 2024 2:30pm - 2:55pm PDT
Grand Ballroom H (Level 1)

Member Day

2:30pm PDT

Profiles Special Interest Group Update - David Weaver, Akeana & James Ball, Qualcomm

Monday October 21, 2024 2:30pm - 2:55pm PDT

Theater (Level 2)

Speakers

James Ball

Qualcomm

David Weaver

Principal Architect, Akeana

Monday October 21, 2024 2:30pm - 2:55pm PDT
Theater (Level 2)

Member Day

3:00pm PDT

Member Day Session: Why Do We Need Yocto Project on RISC-V - Challenges and Best Practices - Khem Raj, Comcast

Monday October 21, 2024 3:00pm - 3:25pm PDT

Grand Ballroom H (Level 1)

Yocto project is a widely adopted standard set of tools and infrastructure for building Embedded systems,
ranging from complex systems based on Linux to RTOS and bare-metal applications.
It's based on OpenEmbedded build technology which has supported RISC-V the architecture from its early days.

The Yocto project has a layered architecture, which provides a scalable mechanism for adding and
customizing new hardware and software support. However, there is a balance required for the best outcome. Core architecture support in the Core layer provides common policies for RISC-V. The architecture layer (meta-riscv) adds additional RISC-V specific customizations and holds support for many SBCs with RISC-V processors.

The Yocto Project has gathered years of experience in deploying into a wide range of products e.g. cars, streaming devices, routers, and cameras to name a few. It is important to leverage these learnings and benefits for the RISC-V ecosystem. This presentation will address the challenges and gaps we have for RISC-V to become tier 1 supported architecture.

In this talk we will provide an overview of how RISC-V is supported in the Yocto project and adjacent layers. Additionally, we will describe the huge opportunity to get RISC-V supported as core architecture. RISC-V is a fast developing architecture. An important aspect of this presentation will be how to get involved in OSS development on RISC-V.

Speakers

Khem Raj

Fellow, Comcast

Khem Raj is a Linux architect at Comcast, helping several open source initiatives within the company: He is guiding the company's adoption of open source software, and becoming an active contributor to the open source components used in the RDK settop software stack. One of the most... Read More →

Monday October 21, 2024 3:00pm - 3:25pm PDT
Grand Ballroom H (Level 1)

Member Day

3:00pm PDT

Privileged Software Horizontal Committee Annual Update - Anup Patel, Ventana Micro Systems

Monday October 21, 2024 3:00pm - 3:25pm PDT

Theater (Level 2)

Speakers

Anup Patel

Principal Software Engineer, Ventana Micro Systems

Anup Patel is an open-source enthusiast with primary interest in hypervisors, firmwares, boot-loaders, and Linux kernel. He has 18+ years of experience developing system level software and he maintains various open-source projects such as OpenSBI, KVM RISC-V, and Xvisor. He is part... Read More →

Monday October 21, 2024 3:00pm - 3:25pm PDT
Theater (Level 2)

Member Day

3:30pm PDT

Member Day Session: A Simple Plan: An API and ABI for Managing Multiple Distinct Sets of Custom Extensions - Guy Lemieux, University of British Columbia

Monday October 21, 2024 3:30pm - 3:55pm PDT

Grand Ballroom H (Level 1)

The RISC-V custom instruction encoding space provides vendors a rich opportunity to innovate. Now, the pending Composable Extensions (CX) Task Group is planning to develop ISA and non-ISA specifications to avoid collisions in opcodes and provide uniform naming, discovery, error handling, context management, and other features that will enable vendors to create a marketplace for composition and reuse of their independently authored custom (instruction) extensions and their software libraries. Instruction set switching is a way to manage this problem. A critical missing piece of the puzzle is the end user perspective: what is the application API, how will the OS manage requests, and what are the implications on the ABI? This presentation outlines a simple plan to address these issues through an API that allows users to allocate and virtualize state context in a uniform manner. We will also discuss the presently manually enforced ABI that keeps the active selector correct at all times while providing backwards compatibility with legacy custom instructions.

Speakers

Guy Lemieux

Professor, University of British Columbia

Guy is a Professor in Computer Engineering at the University of British Columbia where he teaches digital design and computer systems/architecture courses. His research focuses on improving FPGA devices and CAD tools, in particular making them easier to use and more efficient for... Read More →

Monday October 21, 2024 3:30pm - 3:55pm PDT
Grand Ballroom H (Level 1)

Member Day

3:30pm PDT

Member Day Session: Enabling New Security Frontiers: Deep-dive into Implementing Confidential Computing on RISC-V - Ravi Sahita & Atish Patra, Rivos

Monday October 21, 2024 3:30pm - 3:55pm PDT

Theater (Level 2)

This session aims to cover ISA and non-ISA for Confidential VM Environment (CoVE) on RISC-V platforms. The session will describe the use of ratified RISC-V privileged ISA extensions and new priv. ISA extensions called "Supervisor Domains" that are proposed and reaching task group consensus. This session will also describe the specifications for proposed non-ISA/ABI extensions and SoC requirements that enable Confidential Computing on RISC-V-based platforms - and the related open-source activities in open-source that are required to enable the confidential computing stack on RISC-V platforms. The common/abstract aspects that are cross-architectural will be discussed to enable interoperability across different RISC-V and non-RISC-V platforms. A future roadmap of capabilities will be discussed to encourage participation from the community.

Speakers

Ravi Sahita

Principal Security Architect, Rivos Inc.

Atish Patra

Linux kernel Engineer, Rivos

Atish is a Linux kernel engineer working at Rivos . He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing.

Monday October 21, 2024 3:30pm - 3:55pm PDT
Theater (Level 2)

Member Day

4:00pm PDT

Member Day Session: High Assurance Cryptography ISE - G. Richard Newell, Microchip Technology Inc.

Monday October 21, 2024 4:00pm - 4:25pm PDT

Grand Ballroom H (Level 1)

During this session the attendees will learn about the goals, proposals, and status of the High Assurance Cryptography (HAC) Instruction Set Extension (ISE) for RISC-V vector CPUs. While overlapping the functionality of the ratified vector cryptography extensions somewhat, the HAC extensions will provide for better key management – including key encryption – and the possibility for microarchitectures to implement countermeasures against side-channel analysis, thus enabling the HAC instructions to provide secure cryptography in more use cases than the existing instructions. For example, when an adversary can gain close enough physical proximity to the CPU to monitor its electromagnetic emanations during operation, side-channel countermeasures are necessary for secure cryptographic implementations.

What may be of extra interest is that Barry Spinney, an active HAC task group member, is designing a proof-of-concept design of the core cryptographic functional unit, including the optional side-channel countermeasures, and intends to make it fully publicly available as open-source code. This talk will introduce Barry’s design to the audience.

Speakers

G. Richard Newell

Associate Technical Fellow, Microchip Technology

Richard Newell is responsible for architecting the security features for Microchip's current and future generations of FPGAs and SoC FPGAs. Richard has an electrical engineering background with over 45 years of experience in analog and digital signal processing, cryptography, control... Read More →

Monday October 21, 2024 4:00pm - 4:25pm PDT
Grand Ballroom H (Level 1)

Member Day

4:00pm PDT

Technical Steering Committee Meeting

Monday October 21, 2024 4:00pm - 4:25pm PDT

Theater (Level 2)

Monday October 21, 2024 4:00pm - 4:25pm PDT
Theater (Level 2)

Member Day

5:00pm PDT

Member Day Keynotes

Monday October 21, 2024 5:00pm - 6:00pm PDT

Theater (Level 2)

Member Day Closing Keynotes:

Welcome and remarks (Calista 15 min)
Marketing highlights (Andy or Marketing Chair 15 min)
Technical highlights (Krste or Greg/Philipp as Tech Chairs 20 min)
Community highlights (Megan 10 min)

Monday October 21, 2024 5:00pm - 6:00pm PDT
Theater (Level 2)

Member Day