RISC-V Summit

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RISC-V Summit

October 22-23, 2024
Santa Clara, CA
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9:00am PDT

Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International

Tuesday October 22, 2024 9:00am - 9:20am PDT

Mission City Ballroom B2 - B5 (Level 1)

Over the last decade, the industry standard RISC-V Instruction Set Architecture (ISA) has profoundly changed the computing industry with billions of cores shipped and a growing ecosystem of successful businesses all betting their future on RISC-V, but this is only just the beginning. In this session, Calista Redmond will discuss three ways that RISC-V is disrupting and defining the processor industry in the next decade. The ability to customize and extend RISC-V microprocessor designs will usher in an era of workload-defined silicon, where hardware / software co-design enables faster, more efficient compute, optimized for each application. This will power the deployment of AI in mainstream applications, where the flexibility to customize will accelerate innovation and adoption of AI worldwide. This new era of computing will enable developers, industries, and countries to solve local problems, together with access to a global ecosystem and market. Come and discover the future of computing!

Speakers

Calista Redmond

CEO, RISC-V International, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Tuesday October 22, 2024 9:00am - 9:20am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:20am PDT

Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy

Tuesday October 22, 2024 9:20am - 9:35am PDT

Mission City Ballroom B2 - B5 (Level 1)

The XuanTie team is dedicated to advancing RISC-V full-stack hardware and software technologies while fostering a robust ecosystem. Over the past year, we have partnered with industry leaders to deploy innovative RISC-V applications across a wide range of scenarios, from edge to cloud, like edge AI, 5G, laptops, servers, cloud infrastructure and more.

In this presentation, we will share XuanTie's efforts in advanced RISC-V development, including technical exploration in AI and high performance computing, as well how to achieve it by hardware and software co-development. Additionally, we will provide updates on XuanTie products and ecosystem build.

Speakers

Jing Yang

VP of XuanTie, Alibaba DAMO Academy

Jing Yang received her Ph.D. and Master in EECS from UC Berkeley. She is currently the VP of XuanTie at Alibaba DAMO Academy. She is responsible for strategy, product, operation and sales. Her current job focuses on delivering high quality XuanTie products, collaborating internationally... Read More →

Tuesday October 22, 2024 9:20am - 9:35am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:40am PDT

Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA

Tuesday October 22, 2024 9:40am - 10:00am PDT

Mission City Ballroom B2 - B5 (Level 1)

Nine years ago, NVIDIA selected RISC-V for its embedded microcontrollers. Since then, we developed many processors and software stacks, all based on a common underlying hardware and software architecture. Today, every NVIDIA chip comes with multiple embedded RISC-V microcontrollers, each customized for a specific application. In the presentation, we will discuss our architecture as well as several applications. RISC-V’s rich feature set, configurability, extensibility, and active community are reasons why we stand by our 2015 decision to use RISC-V.

Speakers

Frans Sijstermans

Vice President Multimedia Arch/ASIC, NVIDIA

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia... Read More →

Tuesday October 22, 2024 9:40am - 10:00am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:00am PDT

Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology

Tuesday October 22, 2024 10:00am - 10:15am PDT

Mission City Ballroom B2 - B5 (Level 1)

As an open standard, RISC-V architecture has been fast adopted in many major embedded applications, including AI/ML for Cloud and Edge, Automotive, 5G/Networking, MCU/MPU, Multimedia, Storage, Sensor Processing, and Wireless Connectivity. It also started showing up on initial systems of personal computing devices as well as servers. All those applications will continue to be key drivers for global semiconductor industry at least for the next several years and create further opportunity for RISC-V to grow its market share.

In this talk, we will look at RISC-V’s successful stories in various applications. Then we will share our insight of some RISC-V features and ecosystem important for several key technologies behind those applications. We will cover AI/ML acceleration, application processing, embedded and real-time systems, functional safety and security. We will use Andes products as examples for illustration’s purpose.

Speakers

Dr. Charlie Su

President and CTO, Andes Technology

Dr. Charlie Su, Co-founder, CTO and President of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member... Read More →

Tuesday October 22, 2024 10:00am - 10:15am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:15am PDT

Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys

Tuesday October 22, 2024 10:15am - 10:25am PDT

Mission City Ballroom B2 - B5 (Level 1)

Vehicles are undergoing a period of massive evolution driven by increased levels of autonomy, new in-car experiences, and electrification, driving the automotive supply chain to deliver greater innovation while streamlining the product life cycle. RISC-V is the Open Standard Instruction Set Architecture (ISA) that uniquely scales across every in-vehicle compute application, cost effectively delivering innovation opportunities to meet diverse compute requirements that power future generations of vehicles. This session explores how the RISC-V ISA can be used to simplify development and deployment of extensible, power- and area-efficient hardware and software innovation across vehicle ranges and models. It will discuss how RISC-V implementations and ecosystem can offer efficiencies for the automotive supply chain, and the new possibilities it will open up for in-vehicle compute experiences.

Speakers

Rich Collins

Sr. Director Product Management - ARC Processors, Synopsys

Tuesday October 22, 2024 10:15am - 10:25am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:30am PDT

Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology

Tuesday October 22, 2024 10:30am - 10:45am PDT

Mission City Ballroom B2 - B5 (Level 1)

As embedded computing evolves, scalable, high-performance solutions are essential. In this keynote, Mr. Patrick Johnson, Senior Vice President, FPGA and Timing Business Units at Microchip Technology, Inc. will explore the capabilities of Microchip's new 64-bit PIC64 microprocessors. Attendees will learn how these processors handle complex workloads across industrial, automotive, aerospace, and defense sectors.

Discover the unique architecture of the PIC64GX, featuring high-performance RISC-V cores, advanced memory management, and flexible interconnects designed for intelligent edge applications. Key highlights include:

- Enhanced performance, reduced latency, and improved system reliability
- Real-world use cases showcasing the capabilities of PIC64 microprocessors
- Microchip’s MPLAB extension for unified development across multiple ISAs

Gain insights into designing high-performance embedded systems with Microchip's innovative solutions. Join us to explore the future of intelligent edge computing.

Speakers

Patrick Johnson

Sr. Corporate Vice President, Microchip Technology

Patrick Johnson serves as Senior Corporate Vice President at Microchip, where he oversees thecompany's FPGA, Security, Timing, and Touch Screen product lines. Additionally, he acts as theexecutive sponsor for the Aerospace & Defense business segment. Prior to this role, Johnsonwas... Read More →

Tuesday October 22, 2024 10:30am - 10:45am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:15pm PDT

Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework

Tuesday October 22, 2024 4:15pm - 4:30pm PDT

Mission City Ballroom B2 - B5 (Level 1)

The RISC-V ISA is one of the most exciting recent developments in computing with amazing potential to revolutionise applications and industries worldwide. But what does it take to bring consumer products to market based on this young ISA? This session will explore how DeepComputing and their partners worked together to develop a range of products including the first RISC-V based laptop and tablet. It will detail the risk taking, collaboration, learning and accelerated technical development needed to put these products into the hands of consumers worldwide. Come and be inspired, maybe next year’s biggest RISC-V based product could be designed by you.

Speakers

Nirav Patel

Founder and CEO, Framework

Nirav Patel is the Founder and CEO of Framework, makers of the Framework Laptop.

Yuning Liang

CEO, DeepComputing

Yuning is the founder and CEO of Xcalibyte and Advisor of DeepComputing which makes RISC-V SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.Yuning’s career took him from UK to Switzerland to South Korea and finally to China. He comes... Read More →

Tuesday October 22, 2024 4:15pm - 4:30pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:30pm PDT

Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley

Tuesday October 22, 2024 4:30pm - 4:45pm PDT

Mission City Ballroom B2 - B5 (Level 1)

10 years ago, David Patterson and Krste Asanović made the case for RISC-V as an open Instruction Set Architecture with the vision that it become the standard ISA for all computing devices. In this session, David Patterson revisits the arguments we made in that paper and the objections to it at the time then gives his views of the progress made in the subsequent decade and his thoughts on the future.

Speakers

David Patterson

Pardee Professor of Computer Science, Emeritus, University of California at Berkeley

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976.Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of... Read More →

Tuesday October 22, 2024 4:30pm - 4:45pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:50pm PDT

Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted Speers, Microchip; Calista Redmond, RISC-V

Tuesday October 22, 2024 4:50pm - 5:30pm PDT

Mission City Ballroom B2 - B5 (Level 1)

The impact of computing on our modern world is profound, changing our daily life with new ways to communicate, work, and play. Until now, advances in computing have been led by a limited number of companies and countries. RISC-V has changed everything and taken down the barriers to entry. As the industry standard ISA, RISC-V has opened doors for companies big and small, universities and research institutes, and even governments to engage in the global digital economy. RISC-V enables engineers and developers worldwide to innovate locally, with access to a global ecosystem and market. In this panel, we gather experts from around the world to discuss how RISC-V is changing computing in their geography through direct investments, collborations, and incentives to build a bright digital future.

Moderators

Calista Redmond

CEO, RISC-V International, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Speakers

Alessandro Campos

General Coordinator of Semiconductor, Ministry of Science, Technology, Innovations

Alessandro Augusto Nunes Campos, Doctor in Science in Electrical Engineering - Semicon, Bachelor in Computer Engineering and Civil Engineering, worked in research in Aerospace, Information and Communication Technology (ICT), Semiconductors and Engineering. He has taught at renowned... Read More →

Jianying Peng

Co-founder and CEO, Nuclei System Technology

Dr Jianying Peng, graduated from School of Micro-Nano Electronics, Zhejiang University, has more than 15 years of CPU processor design and management experience. Previously Dr Peng worked in Marvell and Synopsys where she led multiple high performance processor designs in ARM and... Read More →

Roger Espasa

CEO & Founder, Semidynamics

Roger Espasa is the founder and CEO of Semidynamics, a European IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected... Read More →

Ted Speers

Technical Fellow, Microchip

Tuesday October 22, 2024 4:50pm - 5:30pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:00am PDT

Keynote: RISC-V State of the Union - Krste Asanović, Chief Architect, RISC-V International

Wednesday October 23, 2024 9:00am - 9:20am PDT

Mission City Ballroom B2 - B5 (Level 1)

In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI, and will outline the programs within the ecosystem that will drive accelerating success for the RISC-V ISA. Krste will discuss the Profiles and Platforms activities enabling the development of software ecosystem support, and the new extensions targeting AI applications.

Speakers

Krste Asanović

Chief Architect, SiFive

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley... Read More →

Wednesday October 23, 2024 9:00am - 9:20am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:20am PDT

Keynote: RISC-V Security - Current Initiatives and Future Trends - Helena Handschuh, Technical Board Advisor

Wednesday October 23, 2024 9:20am - 9:35am PDT

Mission City Ballroom B2 - B5 (Level 1)

In this talk we provide an overview of the must have ingredients to secure todays confidential computing platforms in a world driven by AI: a secure execution environment, a portfolio of strong cryptographic algorithms including the newest post-quantum algorithms, a well-protected and access-controlled memory and secure implementations of all of the above. We then discuss current RISCV Security initiatives in each of these realms and conclude with a view of what's ahead: future trends and how RISCV can help.

Speakers

Helena Handschuh

Technical Board Advisor

Dr. Helena Handschuh is a Technical Board Advisor to security start-ups. Her expertise encompasses embedded and foundational security technologies, crypto and post-quantum crypto, side-channel attacks and countermeasures, security architecture and security standardization. She was... Read More →

Wednesday October 23, 2024 9:20am - 9:35am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:38am PDT

Keynote: Launchpad

Wednesday October 23, 2024 9:38am - 9:58am PDT

Mission City Ballroom B2 - B5 (Level 1)

RISC-V is here!

And with its ability to provide organizations of all sizes with greater flexibility and more opportunity for custom compute, it is rapidly seeing adoption in a wide range of markets from automotive to mobile to data center. Companies around the world are innovating for and on RISC-V to drive the era of open compute. In this session, we will hear directly from companies who have recently launched new solutions helping to power the era of open compute and how RISC-V helps them differentiate.

These are not your ordinary product pitches. Selected companies are given just two minutes to hit the high points and make the case for their new solution.

Moderated by Andrew Moore - Senior Marketing Manager, RISC-V International

Moderators

Andrew Moore

Senior Marketing Manager, RISC-V International

Wednesday October 23, 2024 9:38am - 9:58am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:55am PDT

Keynote Panel: The Future of AI and Security - Andrew Dellow, Qualcomm; Kris Murphy, NVIDIA; Pete Bernard, tinyML Foundation; Pete Warden, Useful Sensors Inc; Andrea Gallo, RISC-V International

Wednesday October 23, 2024 9:55am - 10:25am PDT

Mission City Ballroom B2 - B5 (Level 1)

The growth of new AI algorithms, capabilities and applications is the biggest recent development in computing. New AI algorithms and applications will lead to new considerations for security, both for end users, but also developers and application providers. In this session we talk broadly about how AI and security influence and interact with each other. We discuss the new problems we need to address, how AI can be used for preventative security, the computing capabilities we need to develop to support a fast growing ecosystem and how RISC-V and its ecosystem of members is uniquely positioned to enable AI with security at scale.

Moderators

Andrea Gallo

VP of Technology, RISC-V

Speakers

Andrew Dellow

Director of Engineering, Qualcomm & Chair, RISC-V Security HC, Qualcomm

Kris Murphy

Technical Product Manager, NVIDIA

Pete Bernard

Executive Director, tinyML Foundation

Pete Warden

CEO, Useful Sensors Inc

Wednesday October 23, 2024 9:55am - 10:25am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:30am PDT

Keynote: Mobilizing the Open Source Software Ecosystem for RISC-V - Barna Ibrahim, Vice Chair of RISE Governing Board & Principal, Business Development at Rivos Inc.

Wednesday October 23, 2024 10:30am - 10:45am PDT

Mission City Ballroom B2 - B5 (Level 1)

Join us for a keynote by Barna Ibrahim who explores the strength and diversity of the RISC-V community. As RISC-V rises as the choice of architecture for the AI era, Barna will assess RISC-V's strengths and outline the next steps needed to expand its impact. Building on the success RISC-V has already achieved, the focus now is on preparing the software stack to make RISC-V the default architecture for developers in application processors and custom applications.

Barna will discuss how to support developers by ensuring the RISC-V software ecosystem is robust and ready for production use. She will emphasize the pivotal role that open source developers and maintainers play in this journey and the importance of mobilizing the global community. You’ll gain practical insights into how you can engage with the ecosystem, promote new projects, and contribute to the next stage of RISC-V’s success.
Whether you're a developer, maintainer, or leader, this keynote will inspire you to help shape the future of open computing, where RISC-V isn’t just an alternative, but a powerful choice for driving innovation in the AI era.

Speakers

Barna Ibrahim

BizDev, Vice Chair of RISE Governing Board & Principal, Business Development at Rivos Inc.

Wednesday October 23, 2024 10:30am - 10:45am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

3:55pm PDT

Keynote Panel: The Future of High Performance Computing is RISC-V - Luisa Gonzales, Lawrence Berkeley National Laboratory; Nick Brown, EPCC at the University of Edinburgh; Wei-Han Lien, Tenstorrent Inc.

Wednesday October 23, 2024 3:55pm - 4:40pm PDT

Mission City Ballroom B2 - B5 (Level 1)

RISC-V has seen amazing growth in recent years across a range of applications, with one of the most exciting being High Performance Computing (HPC) where raw computational horsepower is used by scientists and engineers to tackle some of the biggest problems we face worldwide, including weather forecasting and designing more fuel efficient aircraft engines. The possibilities are endless, especially with recent advances in AI enabling new workloads and applications. RISC-V can accelerate the HPC community by providing many more opportunities for compute specialization, delivering increased choice around the architecture, with CPUs tuned for specific workloads, and benefits around integration of accelerators. In this panel we will discuss the huge potential of RISC-V for HPC and how we are making the first generation of RISC-V based supercomputers.

Speakers

Nick Brown

Senior Research Fellow, EPCC at the University of Edinburgh

Dr Nick Brown is a Senior Research Fellow at EPCC, the University of Edinburgh. His main interest is in the role that novel hardware can play in future supercomputers, and is specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively... Read More →

Wei-Han Lien

Chief CPU Architect and Fellow in Machine Learning hardware architecture, Tenstorrent Inc.

Wei-han Lien is a Chief CPU Architect and Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory sub-system for the Tenstorrent heterogeneous high-performance... Read More →

Luisa Gonzales

Research Scientist, Lawrence Berkeley National Laboratory

My research interests include ultra-low-power digital and mixed-signal SoC/ASIC/VLSI design for conventional and non-conventional forms of signal processing. I have also work with FPGA and RISCV for evaluation and exploration of computer architecture. I like to explore emergent technologies... Read More →

Wednesday October 23, 2024 3:55pm - 4:40pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:40pm PDT

Keynote: Community Awards

Wednesday October 23, 2024 4:40pm - 4:55pm PDT

Mission City Ballroom B2 - B5 (Level 1)

Wednesday October 23, 2024 4:40pm - 4:55pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions