RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
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1:55pm PDT

Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here - Jin Kim, Esperanto Technologies

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Grand Ballroom G (Level 1)

The size of the Foundation models behind the Generative AI revolution have grown at a rate of more than 400x every 2 years, while DRAM memory capacity has been increasing only at 2x every two years, leading to what is commonly called the “memory wall”. Similarly, while the required throughput rate of LLMs making up the Foundation models has been increasing at 10x per year, the increase in computational capability of GPUs has been at a pace of only 10x in 4 years, leading to what is commonly called the “compute wall”. These trends have raised a new set of challenges in how to economically train these models, cost-effectively run them, and manage the tremendous increase in electrical power. The first contribution of this session are lessons learned in leveraging hardware and software developed for traditional AI workloads and how it was extended to support Generative AI. The session’s next main contribution is how we are applying lessons learned from our first-generation technology to our next generation. In this session’s final contribution, we will also discuss how the RISC-V ISA could be extended in ways that would make it more efficient and compelling at running Generative AI.

Speakers

Jin Kim

Chief Data Science Officer, Esperanto Technologies

An executive, entrepreneur, and data scientist, Jin’s experience spans enterprise software products and services in AI, big data, and advanced analytics. He has led multinational engineering teams at both established and startup companies, including GraphSQL, Wave Computing, Objectivity... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

2:15pm PDT

Building Tool Chains for RISC-V AI Accelerators - Jeremy Bennett, Embecosm

Tuesday October 22, 2024 2:15pm - 2:33pm PDT

Grand Ballroom G (Level 1)

Our client is developing a massively parallel 64-bit chip for AI inference workloads. To facilitate early software development, we are bringing up an AI tool flow for this chip in a QEMU RISC-V environment. In this talk, we'll share our experience of getting three key AI frameworks working with RISC-V QEMU: Pytorch, Tensorflow and the OpenXLA compiler. Our talk will share our experience addressing two key issues. We will describe the challenges we faced, their solutions and reflect on the lessons learned for future work. The first of these is simply getting the tools to effectively run in an emulated RISC-V environment. These tools are large, fast moving pieces of software with extensive external dependencies. Our second challenge is performance. AI workloads are inherently parallel, and hence run efficiently on vector enabled hardware. However RISC-V vector (RVV) is relatively new, and we experienced difficulty getting the performance we expected out of the tool flow. At the end of this talk, we hope our audience will have a better understanding of the challenges in bringing up an AI tool flow under QEMU. We hope out experience will help them bring up their own AI tool flows.

Speakers

Jeremy Bennett

Chief Executive, Embecosm

Bio: Dr Jeremy Bennett is founder and Chief Executive of Embecosm(http://www.embecosm.com), a consultancy implementing open sourcecompilers, chip simulators and AI/ML for major corporations around the world.He is a author of the standard textbook "Introduction to CompilingTechniques... Read More →

Tuesday October 22, 2024 2:15pm - 2:33pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

2:15pm PDT

An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications - Jamie Kim, Samsung Electronics

Tuesday October 22, 2024 2:15pm - 2:33pm PDT

Grand Ballroom H (Level 1)

I would like to introduce our success story of adopting RISC-V CPU in the embedded domain with the ability to customize the architecture. For this success, we developed a scalable, orthogonal and transparent interrupt architecture which enabled the control of extremely timing-critical tasks. I believe this architecture can be widely adopted across multiple domains with the configurability to adopt to their own requirements.

Speakers

Jamie Kim

Principal Engineer, Samsung Electronics

Jamie Kim received Ph.D. degree on Computer Architecture back in 2015 and has been working in System LSI, Samsung ever since. He led multiple MCU projects using RISC-V, which successfully went to mass production, including the first ever RISC-V based product in Samsung. Currently... Read More →

Tuesday October 22, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

2:15pm PDT

RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS

Tuesday October 22, 2024 2:15pm - 2:53pm PDT

Theater (Level 2)

The RISC-V Foundation's Olympia Performance Model is a great tool as the basis for designing a high-performance RISC-V CPU design. This session will provide a high-level overview of the Olympia Performance Model and then provide examples of how to use the model for tradeoff analysis on different RISC-V Out-of-Order superscalar designs.

Speakers

Knute Lingaard

Sr. Principal Engineer, MIPS

Sr. Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. Lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians and co-chair of the RISC-V International Performance Modeling SIG

Tuesday October 22, 2024 2:15pm - 2:53pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

2:35pm PDT

LLM Inference on RISC-V Embedded CPUs - Yueh-Feng Lee, Andes Technology

Tuesday October 22, 2024 2:35pm - 2:53pm PDT

Grand Ballroom G (Level 1)

The advancement of large language models (LLMs) has significantly enhanced natural language processing capabilities, enabling complex text understanding and generation tasks. This presentation focuses on optimizing the open-source LLaMA CPP project for the RISC-V P extension. By running the TinyLLaMA 1.1B model on the Andes Voyager development board using a quad-core CPU supporting the RISC-V P extension, performance results show that the model can achieve near real-time response. This work highlights the potential of RISC-V as an efficient platform for deploying advanced AI models in resource-constrained environments, contributing to the growing field of edge computing and embedded AI applications.

Speakers

Yueh-Feng Lee

Manager, Andes Technology

Yueh-Feng Lee received his Ph.D. degree in computer science from National Chiao Tung University. He previously worked at Mediatek and Industrial Technology Research Institute. His areas of focus include AI compiler and runtime, hypervisor technology, and embedded systems.

Tuesday October 22, 2024 2:35pm - 2:53pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

2:35pm PDT

Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android - Lev Rumyantsev & Jeremiah Griffin, Google

Tuesday October 22, 2024 2:35pm - 2:53pm PDT

Grand Ballroom H (Level 1)

Berberis is an open source userspace dynamic binary translator facilitating cross-architecture development and testing of RISC-V Android applications. It translates native riscv64 code inside of an Android APK to x86_64 at runtime, enabling developers to test RISC-V builds of their apps on their workstations when target device hardware is unavailable. This presentation will cover the motivation and benefits of userspace translation versus whole-system emulation, the challenges of translating RISC-V code to x86_64, and use cases and future directions for the project.

Speakers

Jeremiah Griffin

Staff Software Engineer, Google

Jeremiah joined Google in 2022 and has been a technical lead of the Berberis RISC-V-to-x86 dynamic binary translator for Android since 2023. His areas of expertise include systems programming, automated testing, embedded and automotive software, and human-machine interfaces. He has... Read More →

Lev Rumyantsev

Software Engineer, Google

Since 2014 Lev has been working at Google on various projects to enhance user experience with Android applications on Large Screen and x86 devices. His main focus has been on developing a binary-translation layer to run ARM-compiled applications on x86 devices. In 2022 Lev also started... Read More →

Tuesday October 22, 2024 2:35pm - 2:53pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

3:15pm PDT

Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension - Markku-Juhani O. Saarinen, Tampere University

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Grand Ballroom H (Level 1)

Version 1.0.0 of the RISC-V Vector Cryptography extensions specification was ratified in late 2023 and adds high-performance cryptography operations to the comprehensive list of ISA features that RISC-V officially supports. We present the first open-source implementation of the RISC-V Vector Cryptography specification, using the PULP Project's Ara vector processor as a baseline and targeting a 28nm technology node. We present the design/verification opportunities and challenges that were encountered. Furthermore, a detailed review of the implementation and benchmarking results will be included in the presentation.

Speakers

Markku-Juhani O. Saarinen

Professor of Practice, Tampere University

Markku-Juhani O. Saarinen is a Professor of Practice (työelämäprofessori) at Tampere University (Finland). A cryptographer by training and with a long international career in security engineering, Markku has co-authored many of the ratified RISC-V cryptography extensions. Currently... Read More →

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

3:15pm PDT

Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Theater (Level 2)

QEMU is an emulator that developers can developer and debug their software on it before getting the real RISC-V hardware. We observed that vectorized executables run much slower than non-vectorized ones on QEMU. From benchmarks (e.g. SPEC CPU2k6 h264), we can see that most of the execution time is occupied by RVV load/store instructions. The same observation has been reported in the QEMU community. For example, the glibc memcpy benchmark runs 2x to 60x slower than its scalar equivalent on QEMU. We aim to improve the performance of RVV instructions in QEMU, thereby reducing the execution time required for tasks such as Android bootup. In this talk, we will provide an overview of how we enhanced the performance of QEMU RVV load/store instructions and discuss future work.

Speakers

Jeremy Bennett

Chief Executive, Embecosm

Max Chou

Engineer, SiFive

Max Chou is a Staff Software - Systems Development Engineer at SiFive. His research interests include binary translation, debugging, optimizations, performance and program analysis tools.

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

11:50am PDT

RISC-V ACPI Is Ready for Server Platforms - Sunil V L & Himanshu Chauhan, Ventana Micro Systems, Inc.

Wednesday October 23, 2024 11:50am - 12:08pm PDT

Grand Ballroom H (Level 1)

ACPI for RISC-V has been under development since 3 years. It has now reached the state where every thing required to fully support ACPI on RISC-V server platforms is available. This talk will provide all the details about the specification changes and software support status for below key features required on server class platforms. 1) Hardware discovery 2) Power / performance management using LPI and CPPC 3) NUMA support 4) CPU-Cache topology information 5) IOMMU support 6) Reliability, Availability and Serviceability (RAS) support 7) Quality of Service Controller support. The talk will enlighten people that RISC-V ACPI ecosystem is ready for adoption.

Speakers

Sunil V L

Software Engineer, Ventana Micro Systems Inc

Sunil is a software engineer working for Ventana Micro Systems. He has been working on ACPI specification updates required for RISC-V as well as its upstream support.

Himanshu Chauhan

Senior Staff Engineer, Ventana Micro Systems, Inc.

Himanshu Chauhan is an open-source software enthusiast with primary interest in hypervisors, Linux kernel, and high-performance computer networks. He has 19+ years of experience developing system level software and data-path for high-performance networking devices. He is part of the... Read More →

Wednesday October 23, 2024 11:50am - 12:08pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

11:50am PDT

RISC-V Control-Flow Integrity (CFI) - Ved Shanbhogue, Rivos & George Christou, Technical University of Crete

Wednesday October 23, 2024 11:50am - 12:28pm PDT

Theater (Level 2)

Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks. This session will provide an overview of how the recently ratified Zicfiss and Zicfilp extensions help defend the programs control flow.

Speakers

Ved Shanbhogue

Member of Technical Staff, Rivos

Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure... Read More →

George Christou

Technical University of Crete

George Christou received his BSc in Computer Science from the University of Crete. His MSc thesis was the design and implementation of hardware assisted Control Flow Integrity for Sparc V8 architecture. His PhD under the supervision of Prof. Sotiris Ioannidis is titled "Hardware-Assisted... Read More →

Wednesday October 23, 2024 11:50am - 12:28pm PDT
Theater (Level 2)

Security

Audience Experience Level Intermediate

12:10pm PDT

Exploration of Productization of Android on RISC-V - Han Mao, Alibaba Damo Academy

Wednesday October 23, 2024 12:10pm - 12:28pm PDT

Grand Ballroom G (Level 1)

Since the Xuantie team promoted the integration of the RISC-V architecture within the AOSP mainline in 2022, the support for RISC-V in the Android system has become increasingly mature. This includes JIT/AOT modes support of Android Runtime, Cuttlefish emulator support, and optimization of numerous third-party libraries. Currently, the productization process of RISC-V Android is still in its early stages, with many upper-layer software stacks yet to achieve full compatibility with RISC-V. To further improve these software stacks, the Xuantie team, along with its partners, has explored productization in various customized scenarios such as payment, cloud desktops, and server clusters. This talk will share typical issues encountered during productization related to performance, stability, power consumption, and application compatibility; as well as how we addressed these issues.

Speakers

Mao Han

Senior Engineer, Alibaba damo academy

Mao Han is working as a Senior Engineer in Alibaba T-Head, covering RISC-V support of Android system. He has many years of experience in Android, Linux, C library and profiling tools. Since 2020, he led a project to port RISC-V architecture onto Android system, and started to served... Read More →

Wednesday October 23, 2024 12:10pm - 12:28pm PDT
Grand Ballroom G (Level 1)

Software

Audience Experience Level Intermediate

1:55pm PDT

GPU Program Support on RISC-V GPU - Hyesoon Kim, Georgia Tech

Wednesday October 23, 2024 1:55pm - 2:13pm PDT

Grand Ballroom G (Level 1)

Describe the software system to support CUDA running

Speakers

Hyesoon Kim

Professor, Georgia Tech

Hyesoon Kim is a professor in the School of Computer Science at the Georgia Institute of Technology and a co-director of the Center for Novel Computing Hierarchy. Her research areas include the intersection of computer architectures and compilers, with an emphasis on heterogeneous... Read More →

Wednesday October 23, 2024 1:55pm - 2:13pm PDT
Grand Ballroom G (Level 1)

Software

Audience Experience Level Intermediate

2:15pm PDT

RISC-V RAS Error-Record Register Interface (RERI) - Greg Favor, Ventana Micro Systems

Wednesday October 23, 2024 2:15pm - 2:33pm PDT

Grand Ballroom H (Level 1)

The recently ratified RERI specification provides a open and standardized register interface specification for error reporting for RISC-V based designs targeting segments from HPC to embedded.

Speakers

Greg Favor

CTO, Ventana Micro Systems

Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing... Read More →

Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

2:15pm PDT

Hardening Linux and FreeBSD on RISC-V with CHERI - Carl Shaw, Codasip

Wednesday October 23, 2024 2:15pm - 2:33pm PDT

Theater (Level 2)

CHERI is an emerging security technology, jointly developed over the last decade by the University of Cambridge and SRI International. In this talk, we will describe the work being done to bring CHERI support to FreeBSD and Linux on RISC-V, where we can provide both memory safety as well as isolating software components to improve run-time safety, security and robustness.

Speakers

Carl Shaw

Safety and Security Manager, Codasip

Prior to joining Codasip, Carl has provided security engineering and architecture consultancy to leading global electronics and semiconductor companies for more than 15 years. With a Physics Ph.D., and a career mixing electronics design in government defense, and OS and firmware development... Read More →

Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Theater (Level 2)

Security

Audience Experience Level Intermediate

2:15pm PDT

Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs - Jon Taylor, Synopsys

Wednesday October 23, 2024 2:15pm - 2:33pm PDT

Grand Ballroom G (Level 1)

RISC-V allows the freedom to innovate with custom instructions but working out which custom instructions add the most value is key to success and more easily done with simulation and models than RTL. At the same time new applications such as AI/ML are creating ever more complex SoCs with very high core counts. Using models in a digital twin of the design allows fast architectural exploration, accelerates software development and post silicon can help with DevOps flows and diagnosing in-field failures. This talk discusses two custom SoC projects where virtual platforms have been used to successfully develop software for many core systems in advance of silicon being available. This requires fast, accurate golden models of the CPUs in a simulation environment which can scale to hundreds or more cores.

Speakers

Jon Taylor

Senior Director of Product Management, Synopsys

Jon has over 20 years of experience in the semiconductor industry, working in technical areas from CPU verification to embedded software, and commercial areas including field applications and technology strategy. He has worked on multiple architectures including Arm, RISC-V and proprietary... Read More →

Wednesday October 23, 2024 2:15pm - 2:33pm PDT
Grand Ballroom G (Level 1)

Software

Audience Experience Level Intermediate

2:35pm PDT

Open-Source Commercial-Grade RISC-V IOMMU with Verification - Manuel Rodriguez, Zero-Day Labs & Saad Waheed, 10xEngineers

Wednesday October 23, 2024 2:35pm - 2:53pm PDT

Grand Ballroom H (Level 1)

This session provides an in-depth overview of a highly parameterizable open-source IOMMU IP compliant with the RISC-V IOMMU Specification v1.0. The IP was developed by Zero-Day Labs and is currently being verified in collaborative efforts with 10xEngineers. The presentation covers the implementation details of the IP, which includes features like two-stage address translation, MSI translation support, and internal IO Address Translation Caches (IOATCs) for improved performance. We discuss the verification process carried out in collaboration with 10xEngineers, which has achieved 85% of coverage targets and addressed several RTL bugs and design issues. Additionally, the session highlights the current applications of this IP in projects such as the AlSaqr 2.0 platform for autonomous nano-UAVs and the PULP Carfield architecture. The session concludes with future work plans (e.g., completing the verification and performing design optimizations) and opportunities for community collaboration to enhance the IP further.

Speakers

Saad Waheed

Manager/ Sr. Verification Engineer, 10xEngineers

Saad Waheed is a Sr. Verification Engineer and Manager at 10xEngineers. His expertise lies in the domain of design verification of RISC-V based processors and SoCs. His prior experience includes working with SiFive on the verification of its RISC-V cores for the Core IP 21G1 release... Read More →

Manuel Rodriguez

PhD Student / Hardware Architect, Zero-Day Labs

Manuel Rodríguez earned his M.Sc. degree in Electronic and Computer Engineering from the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. at the same institution. Additionally, he works as a hardware architect... Read More →

Wednesday October 23, 2024 2:35pm - 2:53pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Intermediate

2:35pm PDT

Porting SLEEF to RISC-V - Ludovic Henry, Rivos & Eric Love, SiFive

Wednesday October 23, 2024 2:35pm - 2:53pm PDT

Grand Ballroom G (Level 1)

Join us as we explore the journey of porting the SLEEF vectorized math library to the RISC-V architecture, focused on ensuring complete support for single, double, and quad precision math operations, Discrete Fourier Transforms (DFT), and testing all of it on QEMU on GitHub Actions.

Speakers

Eric Love

Algorithms & Libraries Team, SiFive

Ludovic Henry

Software Engineer & Lead, Rivos

I am the lead for the Managed Runtimes and System Libraries team at Rivos, a RISC-V hardware focused company. I contribute to many projects, making sure they are well supported on RISC-V. I’m also the lead for the Language Runtimes working group at RISE.

Wednesday October 23, 2024 2:35pm - 2:53pm PDT
Grand Ballroom G (Level 1)

Software

Audience Experience Level Intermediate