RISC-V Summit

There has been huge interest in building accelerators for AI in the decade since AlexNet ushered in the current deep learning revolution. Billions of dollars in capital have been committed, and many ambitious projects have been launched, across established manufacturers, hyperscalers, and startups. In this talk, we will reflect on our experiences at Google designing and deploying successful accelerators and the different ways that subtle challenges make effective acceleration hard. RISC-V potentially helps with these challenges, while lowering barriers to entry, reducing risks, and sharing the benefit of expertise and experience. We will make connections between our experiences and how RISC-V accelerates accelerator development itself, highlighting how the shared work on a RISC-V ecosystem for deep learning acceleration can be positive-sum, benefiting all who participate.

Traditional post silicon HW debug data collection involves the gathering of a snapshot of the design state at the point of failure using scan and an array dump. We propose a hardware mechanism called Debug Signal Trace (DST) that provides the ability to trace a set of design signals over multiple cycles leading to the point of the failure and to store the trace to an on-chip memory like SRAM, or to off-chip System memory. Post processing of the stored debug trace data not only gives debug visibility, but also the ability to build post silicon coverage points. Debug Signal Trace data is timestamped to correlate with instruction trace data. This extends the use-case to SW performance analysis. To ease adoption and usability, the DST control register definition mirrors that of the RISC-V Trace Control Interface which is familiar to the RISC-V debug community. DST supports signal compression to minimize the memory storage footprint. DST leverages the triggers specified in RISC-V Debug Spec while adding user configurable triggers using a select set of design signals.

With the increased usage of RISC-V processors across the whole range of SoC market segments, quality of the RISC-V processor is an increasingly important issue. Historically, processor IP has been purchased from single-source vendors who own the ISA, and this IP was assumed to be of excellent quality. However, in the RISC-V ecosystem with vendor-supplied IP, open source IP and IP developed in-house, such quality cannot be taken for granted. This creates a verification “disconnect” between SoC developers expecting high-quality IP and processor developers that do not have the verification resources of the single source processor IP vendors. This talk will discuss how dynamic and formal methods can be used together for a more thorough and efficient verification process, helping to bridge the verification disconnect. Examples of using this combined methodology on open-source cores from OpenHW Group, specifically the CV32E40 family, CVW and CVA6, will be presented, including functional coverage results. A key feature of the RISC-V ISA is its extensibility, enabling custom instructions and CSRs to be added. The combined approach will also be shown to work well in this common situation.

The Unformatted Trace and Diagnostic Data Packet Encapsulation for RISC-V specification was recently ratified. The standard was developed in response to a need for a standard encapsulation format for Efficient Trace for RISC-V (E-Trace) packets, that would support a variety of widely used transport protocols. However, the resulting standard is broader than this, and is suitable for encapsulating any kind of unformatted diagnostic data.

This presentation explores the properties and benefits of this standard and shows how it can be applied to E-Trace (as well as other types of diagnostic data such as bus utilization metrics, bus or logic analyzer trace and code profiling instrumentation) for transport via AMBA ATB or the Siemens Messaging Infrastructure.

This session covers how simultaneous multithreading (SMT) with RISC-V Hardware threads (harts) increases the throughput efficiency of a processing subsystem for automotive applications.