RISC-V Summit

The automotive industry is experiencing a massive paradigm shift. Cars are becoming increasingly autonomous, connected, and computerized. Modern E/E-architectures are pushing for an unforeseen functionality integration density, resulting in physically separate ECUs becoming virtualized and mapped to logical partitions within a single physical MCU. While functional safety has been pivotal for vehicle certification for decades, this increasing connectivity have shed light on the need for (cyber-)security and paved the way for the release of the new standard ISO21434. RISC-V has a pivotal opportunity to transform automotive computing systems, but we argue that current ISA / extensions are not ready yet. This talk provides our critical perspective on the existing limitations, particularly the upcoming WorldGuard technology, to address virtualized MCU requirements per foreseen automotive applications. We then present our proposal to address such limitations, mainly targeting master-side protection. We complete the talk by explaining the roadmap towards a full open-source Proof-of-Concept, which includes extending QEMU, an open-source RISC-V Core, and building a complete software stack.

In this talk I will present ongoing work as part of the RISC-V golden model working group to develop and maintain the Sail language and  golden reference model for the RISC-V ISA. Sail is an open-source domain-specific language for ISA design and definition, which supports many use-cases, including documentation, use as a reference simulator, relaxed-concurrency semantics, hardware verification, and more.

This talk will describe our vision for the future of the RISC-V golden model. There are many challenges faced by model developers, such as the vast ecosystem of extensions and configurable options supported by RISC-V. We also need to provide a model that is more broadly useful as a source of documentation and learning for the wider RISC-V community.
I will discuss solutions for these challenges, which we intend to address both within the golden model itself, and by co-evolving Sail language itself to better support the unique needs of RISC-V. For example, we are introducing a module system for organising RISC-V extensions, a unified configuration system that supports all the aforementioned Sail use-cases, and enhanced Asciidoctor support for documentation integration.

By presenting this talk, I also hope to be able to engage further with attendees regarding their needs from a golden model.

In embedded system development, several technical issues need to be solved to facilitate the transition from another architecture to RISC-V. For example, in existing embedded devices, there are products with multiple OSs, including RTOS. In such products, hardware virtualization is used to run General Purpose OS(GPOS) and RTOS to guarantee real-time performance and use GPOS software assets. However, some OSs (especially RTOS) are not intended to run on virtual machines. Therefore, we are researching a mechanism that enables all RTOSs to run even on a RISC-V virtual machine. In this talk, we will provide strategies for running the RTOS on virtual machines and the issues to be solved for its practical use.

The Zilsd & Zclsd extensions provide load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings. The extensions are expected to be implemented in all kinds of embedded processors, with optimal performance being reached in core with a data bus of at least 64 bit - a property commonly given in superscalar implementations. The impact on code size of this extension is discussed in detail, leading to recommendations for future compiler improvements.

In last year’s North America Summit, Dr. Jianying Peng presented Nuclei’s NA900 (automotive) RISC-V core as the world’s 1st ASIL-D product certified RISC-V core in the automotive session. For the past 1 year, Nuclei has continued to develop functional safety solution including world’s 2nd ASIL-D product certified RISC-V core NA300 and bus fabric with safety features. Nuclei has extended the scope to information security as well. Beyond RISC-V core and bus fabric, Nuclei has released HSM (hardware security module) based on RISC-V core recently. By doing this, the position of RISC-V in the automotive ecosystem has been further strengthened with a comprehensive set of combined RISC-V based security & functional safety solutions. Thus this year we would like to share 4 topics from technical, ecosystem and business perspectives: 1. Nuclei’s experience in functional safety and security design 2. Nuclei’s experience in automotive SoC design 3. Automotive electronics software ecosystem 4. Customer success stories and open concern of RISC-V from different customers we see in the past 2 years.

Mission Critical Edge Compute demands high-performance MPUs with time and space partitioning capabilities to enable mixed-criticality workloads. As well, the MPUs must be built with comprehensive fault-tolerance and fault-isolation capabilities. Given these requirements, A&D and Industrial systems developers worldwide are looking to RISC-V as a key enabling technology to enable their next-generation platforms. This presentation will explore: 1) Why RISC-V for Mission Critical Edge Compute: Virtualization, Vector Processing, and WorldGuard Partitioning 2) How RISC-V is set to transform space computing 3) The opportunities for RISC-V in aviation 4) Applications for RISC-V in industrial applications This presentation will conclude with how Microchip is responding and a call-to-action for what is needed from the RISC-V ecosystem to fully capitalize on this once in a generation opportunity to transform critical infrastructure.

RISC-V's open standard provides a great opportunity to democratize the Domain Specific Processor market. Over the last twenty to thirty years, the processor market was dominated by general purpose closed-architectures. This environment limited processor engineering companies and job prospects. RISC-V enables a new going to market strategy that is not linked to a limited number of processor vendors, but a market strategy where the application and processor integrator defines and develops the Domain Specific Processor, the traditional System-On-Chip (SoC) developer. To extend custom processing to the larger segment of SoC developers, new processor engineers are required. Due to the lack of previous job prospects, there is a processor engineering shortage to sustain the pace of innovation. The RISC-V ecosystem is coming to the rescue. By developing processor Bounded Customization models where the Software Engineer uses standard software programming practices to architect and to develop custom processors, the inadequate supply of processor engineers can be solved. Who better than the application and algorithm engineer to become tomorrow's processor engineer.

The success of the RISC-V instruction set architecture depends on the ability for software to exploit the hardware effectively, both for the baseline (and now defined ISA profiles) and for new instruction set extensions. The LLVM compiler infrastructure (including Clang) is key for this, and has been a major success story for RISC-V software ecosystem enablement through cross-party collaboration. This talk provides an update on the current status, with up to date benchmarks for code size and generated code performance vs GCC. We'll explore how recent work in CI and tracking of these metrics has been helping to accelerate progress and ensure quality, and look ahead to future challenges.

A set of RISC-V Trace specifications developed by N-Trace TG has been recently ratified. It consists of three separated, but interconnected specifications: * RISC-V N-Trace (Nexus based) Trace Specification * RISC-V Trace Control Specification * RISC-V Trace Connectors Specification This session will explain key trace concepts and solutions. Relations to different existing trace standards will be highlighted. Practical use-cases, implementation hints and difficulties will be elaborated. Future development and possible enhancements will be mentioned.

In this talk, we will introduce the latest work we've done on matrix extension instructions (AME), the AI software stack for the first mass production RISC-V NPU card based on matrix, and the real commercial application cases in one 1000P computing center using large models. 1. As one of the first companies in the world to submit matrix extension proposals to the Foundation, we gained a lot of implementation experience on our first mass production NPU card STCP920, would like to share with audience about how we design and use some of instructions, as well as recent works in AME. 2. Based on STCP920, we completed a full software stack for AI application, will discuss some challages we encountered on LLVM, AI compiler and operators for example. 3. We just made a big win in one 1000P computing center project using NPU card, would like to share how to use RISC-V AI accelerator to build it, what's the strength and opportunities for RISC-V, what's the senario and application for AI. Generally speaking, we believe to provide computing power means to provide service.