RISC-V Summit

Ensuring security in Central Processing Units (CPUs) has become a critical concern. This presentation examines the importance of CPU security in the context of RISC-V , with a focus on addressing potential vulnerabilities through various security measures. In the presentation we explore and analyze different types of cyber-attacks relevant to RISC-V CPUs, such as code injection, buffer overflows and jump-orienting programming but also cyber-physical attacks like side-channel attacks, fault injections, and supply chain attacks such as hardware Trojans. We discuss the concept of Lockstep as a redundancy technique and Code & Control-Flow Integrity verification (CCFI) to enhance security and safety by detecting and correcting errors or malicious manipulations. Additionally, the presentation emphasizes the significance of industry-standard certifications (Common Criteria, FIPS 140-3) in verifying the effectiveness of security solutions. Finally, we explain why, by understanding and implementing robust security measures, RISC-V CPUs can establish a strong foundation for secure computing environments, safeguarding against diverse cyber threats and risks.

This deep dive will explain an end to end software stack solution to RISC-V based AI chips, including an innovation way to write AI kernels with new programming languages such as Triton (and Mojo later), using MLIR/LLVM based AI compiler infra to lower Triton kernels and neural networks from frameworks such as Pytorch, ONNX, Tensorflow and JAX into a range of high/middle/low level of MLIR dialects to do coarse grained high level optimizations such as loop tiling, kernel fusion, auto-vectorization etc. This paves the way of sharing common open source Triton kernels libraries provided in PyTorch and other frameworks, and greatly reduces the adoption time for AI software stack to RISC-V based AI chip. This talk will also explore the limitation of Triton language, and how can we extend the Triton language, and also the MLIR conversion and optimization passes to better support non GPU architecture target such as RISC-V.

Join us to explore the RISC-V Server Ecosystem enablement discussion, a standardization effort to ensure compatibility and reliability across RISC-V server SoCs. This talk will cover key hardware capabilities, including harts, timers, PCIe root complexes, and management features, and explain how this specification simplifies OS and hypervisor support. Attendees will learn about the collaborative efforts and partnerships driving this initiative and its impact on high-performance server applications. Discover how this work will shape the future of RISC-V in server computing.specification.

Historically, software developers have been forced to use special compiler switches to instrument code to gather traces and performance information. This has three disadvantages: it requires recompilation of the code to include the instrumentation, it increases code size, and it affects/distorts execution timing of the program. SiFive has developed a new approach, SiFive® Event Trace. Event Trace is unique in that it provides front-end hardware filtering to selectively capture specific events as the RISC-V core executes programs in real time. No software instrumentation or recompilation is required, saving development and debug time while avoiding the overhead and timing distortion that can result from software instrumentation. SiFive Event Trace is flexible, allowing developers to choose events to capture, including calls/returns, exceptions, interrupts, context changes, watchpoints, external triggers, and more. Each trace event has a high-resolution timestamp that provides both duration and interval timing, and This session will give developers a complete overview of this innovative profiling solution and demonstrate how to configure, view, and interpret Event Traces

We will give the latest performance evaluation of the main Post-Quantum Cryptography standards, Kyber and Dilithium, on RISC-V Vector Architecture and discuss possibilities for speeding it up further with new instructions. Due to its 1600-bit state size, a fast SHA3 / Keccak instruction would require slightly unusual architectural features from a vector processor. Based on hardware and software experiments and benchmarks, we argue that performance returns in Post-Quantum Cryptography still make it worthwhile for many common use cases, such as content delivery servers performing a lot of TLS handshakes.

Many libraries, such as OpenCV, FFmpeg, XNNPACK, and Eigen, utilize Arm or x86 SIMD Intrinsics to optimize programs for performance. With the emergence of RISC-V Vector Extensions (RVV), there is a need to migrate these performance legacy codes for RVV. Our prior work at RISC-V Summit 2023, USA, successfully enhanced the open-source library, SIMD Everywhere (SIMDe), to support the migration from ARM NEON to RISC-V Vector Extensions. In this talk, we will update the status of our open source upstream at SIMDe. In addition, we further explore the migration of quantum-secure encryption algorithms with the RISC-V Cryptography Extension to meet the needs of post-quantum cryptography. Through these efforts, we identify a critical issue: the translation of SIMD intrinsics often fails to utilize the wider vectors available on the target platform. To address this issue, we propose an aggregation optimization in the LLVM pass that collects short vector intrinsics to fully leverage the wider vectors provided by RISC-V vector extension. Our vector aggregation optimization further boosts performance of RVV-enhanced SIMDe from 4.350× to 11.020×.