RISC-V Summit

RISC-V's open standard provides a great opportunity to democratize the Domain Specific Processor market. Over the last twenty to thirty years, the processor market was dominated by general purpose closed-architectures. This environment limited processor engineering companies and job prospects. RISC-V enables a new going to market strategy that is not linked to a limited number of processor vendors, but a market strategy where the application and processor integrator defines and develops the Domain Specific Processor, the traditional System-On-Chip (SoC) developer. To extend custom processing to the larger segment of SoC developers, new processor engineers are required. Due to the lack of previous job prospects, there is a processor engineering shortage to sustain the pace of innovation. The RISC-V ecosystem is coming to the rescue. By developing processor Bounded Customization models where the Software Engineer uses standard software programming practices to architect and to develop custom processors, the inadequate supply of processor engineers can be solved. Who better than the application and algorithm engineer to become tomorrow's processor engineer.

Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks. This session will provide an overview of how the recently ratified Zicfiss and Zicfilp extensions help defend the programs control flow.

The Unformatted Trace and Diagnostic Data Packet Encapsulation for RISC-V specification was recently ratified. The standard was developed in response to a need for a standard encapsulation format for Efficient Trace for RISC-V (E-Trace) packets, that would support a variety of widely used transport protocols. However, the resulting standard is broader than this, and is suitable for encapsulating any kind of unformatted diagnostic data.

This presentation explores the properties and benefits of this standard and shows how it can be applied to E-Trace (as well as other types of diagnostic data such as bus utilization metrics, bus or logic analyzer trace and code profiling instrumentation) for transport via AMBA ATB or the Siemens Messaging Infrastructure.

CHERI is an emerging security technology, jointly developed over the last decade by the University of Cambridge and SRI International. In this talk, we will describe the work being done to bring CHERI support to FreeBSD and Linux on RISC-V, where we can provide both memory safety as well as isolating software components to improve run-time safety, security and robustness.

We will give the latest performance evaluation of the main Post-Quantum Cryptography standards, Kyber and Dilithium, on RISC-V Vector Architecture and discuss possibilities for speeding it up further with new instructions. Due to its 1600-bit state size, a fast SHA3 / Keccak instruction would require slightly unusual architectural features from a vector processor. Based on hardware and software experiments and benchmarks, we argue that performance returns in Post-Quantum Cryptography still make it worthwhile for many common use cases, such as content delivery servers performing a lot of TLS handshakes.