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In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI, and will outline the programs within the ecosystem that will drive accelerating success for the RISC-V ISA. Krste will discuss the Profiles and Platforms activities enabling the development of software ecosystem support, and the new extensions targeting AI applications.
Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley... Read More →
In this talk we provide an overview of the must have ingredients to secure todays confidential computing platforms in a world driven by AI: a secure execution environment, a portfolio of strong cryptographic algorithms including the newest post-quantum algorithms, a well-protected and access-controlled memory and secure implementations of all of the above. We then discuss current RISCV Security initiatives in each of these realms and conclude with a view of what's ahead: future trends and how RISCV can help.
Dr. Helena Handschuh is a Technical Board Advisor to security start-ups. Her expertise encompasses embedded and foundational security technologies, crypto and post-quantum crypto, side-channel attacks and countermeasures, security architecture and security standardization. She was... Read More →
And with its ability to provide organizations of all sizes with greater flexibility and more opportunity for custom compute, it is rapidly seeing adoption in a wide range of markets from automotive to mobile to data center. Companies around the world are innovating for and on RISC-V to drive the era of open compute. In this session, we will hear directly from companies who have recently launched new solutions helping to power the era of open compute and how RISC-V helps them differentiate.
These are not your ordinary product pitches. Selected companies are given just two minutes to hit the high points and make the case for their new solution.
Moderated by Andrew Moore - Senior Marketing Manager, RISC-V International
The growth of new AI algorithms, capabilities and applications is the biggest recent development in computing. New AI algorithms and applications will lead to new considerations for security, both for end users, but also developers and application providers. In this session we talk broadly about how AI and security influence and interact with each other. We discuss the new problems we need to address, how AI can be used for preventative security, the computing capabilities we need to develop to support a fast growing ecosystem and how RISC-V and its ecosystem of members is uniquely positioned to enable AI with security at scale.
Join us for a keynote by Barna Ibrahim who explores the strength and diversity of the RISC-V community. As RISC-V rises as the choice of architecture for the AI era, Barna will assess RISC-V's strengths and outline the next steps needed to expand its impact. Building on the success RISC-V has already achieved, the focus now is on preparing the software stack to make RISC-V the default architecture for developers in application processors and custom applications.
Barna will discuss how to support developers by ensuring the RISC-V software ecosystem is robust and ready for production use. She will emphasize the pivotal role that open source developers and maintainers play in this journey and the importance of mobilizing the global community. You’ll gain practical insights into how you can engage with the ecosystem, promote new projects, and contribute to the next stage of RISC-V’s success. Whether you're a developer, maintainer, or leader, this keynote will inspire you to help shape the future of open computing, where RISC-V isn’t just an alternative, but a powerful choice for driving innovation in the AI era.
RISC-V has seen amazing growth in recent years across a range of applications, with one of the most exciting being High Performance Computing (HPC) where raw computational horsepower is used by scientists and engineers to tackle some of the biggest problems we face worldwide, including weather forecasting and designing more fuel efficient aircraft engines. The possibilities are endless, especially with recent advances in AI enabling new workloads and applications. RISC-V can accelerate the HPC community by providing many more opportunities for compute specialization, delivering increased choice around the architecture, with CPUs tuned for specific workloads, and benefits around integration of accelerators. In this panel we will discuss the huge potential of RISC-V for HPC and how we are making the first generation of RISC-V based supercomputers.
Senior Research Fellow, EPCC at the University of Edinburgh
Dr Nick Brown is a Senior Research Fellow at EPCC, the University of Edinburgh. His main interest is in the role that novel hardware can play in future supercomputers, and is specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively... Read More →
Chief CPU Architect and Fellow in Machine Learning hardware architecture, Tenstorrent Inc.
Wei-han Lien is a Chief CPU Architect and Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory sub-system for the Tenstorrent heterogeneous high-performance... Read More →
Research Scientist, Lawrence Berkeley National Laboratory
My research interests include ultra-low-power digital and mixed-signal SoC/ASIC/VLSI design for conventional and non-conventional forms of signal processing. I have also work with FPGA and RISCV for evaluation and exploration of computer architecture. I like to explore emergent technologies... Read More →