RISC-V Summit

Join us to explore the RISC-V Server Ecosystem enablement discussion, a standardization effort to ensure compatibility and reliability across RISC-V server SoCs. This talk will cover key hardware capabilities, including harts, timers, PCIe root complexes, and management features, and explain how this specification simplifies OS and hypervisor support. Attendees will learn about the collaborative efforts and partnerships driving this initiative and its impact on high-performance server applications. Discover how this work will shape the future of RISC-V in server computing.specification.

ACPI for RISC-V has been under development since 3 years. It has now reached the state where every thing required to fully support ACPI on RISC-V server platforms is available. This talk will provide all the details about the specification changes and software support status for below key features required on server class platforms. 1) Hardware discovery 2) Power / performance management using LPI and CPPC 3) NUMA support 4) CPU-Cache topology information 5) IOMMU support 6) Reliability, Availability and Serviceability (RAS) support 7) Quality of Service Controller support. The talk will enlighten people that RISC-V ACPI ecosystem is ready for adoption.

A set of RISC-V Trace specifications developed by N-Trace TG has been recently ratified. It consists of three separated, but interconnected specifications: * RISC-V N-Trace (Nexus based) Trace Specification * RISC-V Trace Control Specification * RISC-V Trace Connectors Specification This session will explain key trace concepts and solutions. Relations to different existing trace standards will be highlighted. Practical use-cases, implementation hints and difficulties will be elaborated. Future development and possible enhancements will be mentioned.

In this talk, we will introduce the latest work we've done on matrix extension instructions (AME), the AI software stack for the first mass production RISC-V NPU card based on matrix, and the real commercial application cases in one 1000P computing center using large models. 1. As one of the first companies in the world to submit matrix extension proposals to the Foundation, we gained a lot of implementation experience on our first mass production NPU card STCP920, would like to share with audience about how we design and use some of instructions, as well as recent works in AME. 2. Based on STCP920, we completed a full software stack for AI application, will discuss some challages we encountered on LLVM, AI compiler and operators for example. 3. We just made a big win in one 1000P computing center project using NPU card, would like to share how to use RISC-V AI accelerator to build it, what's the strength and opportunities for RISC-V, what's the senario and application for AI. Generally speaking, we believe to provide computing power means to provide service.

The recently ratified RERI specification provides a open and standardized register interface specification for error reporting for RISC-V based designs targeting segments from HPC to embedded.

This session provides an in-depth overview of a highly parameterizable open-source IOMMU IP compliant with the RISC-V IOMMU Specification v1.0. The IP was developed by Zero-Day Labs and is currently being verified in collaborative efforts with 10xEngineers. The presentation covers the implementation details of the IP, which includes features like two-stage address translation, MSI translation support, and internal IO Address Translation Caches (IOATCs) for improved performance. We discuss the verification process carried out in collaboration with 10xEngineers, which has achieved 85% of coverage targets and addressed several RTL bugs and design issues. Additionally, the session highlights the current applications of this IP in projects such as the AlSaqr 2.0 platform for autonomous nano-UAVs and the PULP Carfield architecture. The session concludes with future work plans (e.g., completing the verification and performing design optimizations) and opportunities for community collaboration to enhance the IP further.

This session covers how simultaneous multithreading (SMT) with RISC-V Hardware threads (harts) increases the throughput efficiency of a processing subsystem for automotive applications.