RISC-V Summit

The Google Collaboration Breakfast will be a software-focused panel discussion with David Patterson, Lars Bergstrom and Andrea Gallo with Amber Huffman as moderator.

No pre-registration is required to attend. We do our best to accommodate everyone interested in joining, but please note that participation is on a first-come, first-served basis.

Historically, software developers have been forced to use special compiler switches to instrument code to gather traces and performance information. This has three disadvantages: it requires recompilation of the code to include the instrumentation, it increases code size, and it affects/distorts execution timing of the program. SiFive has developed a new approach, SiFive® Event Trace. Event Trace is unique in that it provides front-end hardware filtering to selectively capture specific events as the RISC-V core executes programs in real time. No software instrumentation or recompilation is required, saving development and debug time while avoiding the overhead and timing distortion that can result from software instrumentation. SiFive Event Trace is flexible, allowing developers to choose events to capture, including calls/returns, exceptions, interrupts, context changes, watchpoints, external triggers, and more. Each trace event has a high-resolution timestamp that provides both duration and interval timing, and This session will give developers a complete overview of this innovative profiling solution and demonstrate how to configure, view, and interpret Event Traces

The success of the RISC-V instruction set architecture depends on the ability for software to exploit the hardware effectively, both for the baseline (and now defined ISA profiles) and for new instruction set extensions. The LLVM compiler infrastructure (including Clang) is key for this, and has been a major success story for RISC-V software ecosystem enablement through cross-party collaboration. This talk provides an update on the current status, with up to date benchmarks for code size and generated code performance vs GCC. We'll explore how recent work in CI and tracking of these metrics has been helping to accelerate progress and ensure quality, and look ahead to future challenges.

Since the Xuantie team promoted the integration of the RISC-V architecture within the AOSP mainline in 2022, the support for RISC-V in the Android system has become increasingly mature. This includes JIT/AOT modes support of Android Runtime, Cuttlefish emulator support, and optimization of numerous third-party libraries. Currently, the productization process of RISC-V Android is still in its early stages, with many upper-layer software stacks yet to achieve full compatibility with RISC-V. To further improve these software stacks, the Xuantie team, along with its partners, has explored productization in various customized scenarios such as payment, cloud desktops, and server clusters. This talk will share typical issues encountered during productization related to performance, stability, power consumption, and application compatibility; as well as how we addressed these issues.

Describe the software system to support CUDA running

RISC-V allows the freedom to innovate with custom instructions but working out which custom instructions add the most value is key to success and more easily done with simulation and models than RTL. At the same time new applications such as AI/ML are creating ever more complex SoCs with very high core counts. Using models in a digital twin of the design allows fast architectural exploration, accelerates software development and post silicon can help with DevOps flows and diagnosing in-field failures. This talk discusses two custom SoC projects where virtual platforms have been used to successfully develop software for many core systems in advance of silicon being available. This requires fast, accurate golden models of the CPUs in a simulation environment which can scale to hundreds or more cores.

Join us as we explore the journey of porting the SLEEF vectorized math library to the RISC-V architecture, focused on ensuring complete support for single, double, and quad precision math operations, Discrete Fourier Transforms (DFT), and testing all of it on QEMU on GitHub Actions.

Many libraries, such as OpenCV, FFmpeg, XNNPACK, and Eigen, utilize Arm or x86 SIMD Intrinsics to optimize programs for performance. With the emergence of RISC-V Vector Extensions (RVV), there is a need to migrate these performance legacy codes for RVV. Our prior work at RISC-V Summit 2023, USA, successfully enhanced the open-source library, SIMD Everywhere (SIMDe), to support the migration from ARM NEON to RISC-V Vector Extensions. In this talk, we will update the status of our open source upstream at SIMDe. In addition, we further explore the migration of quantum-secure encryption algorithms with the RISC-V Cryptography Extension to meet the needs of post-quantum cryptography. Through these efforts, we identify a critical issue: the translation of SIMD intrinsics often fails to utilize the wider vectors available on the target platform. To address this issue, we propose an aggregation optimization in the LLVM pass that collects short vector intrinsics to fully leverage the wider vectors provided by RISC-V vector extension. Our vector aggregation optimization further boosts performance of RVV-enhanced SIMDe from 4.350× to 11.020×.