RISC-V Summit

 In this session, Microchip will introduce the PIC64 series of 64-bit microprocessors which are built to empower and enable innovation from the industrial edge to the edge of space. We will showcase a video processing demonstration on the PIC64GX MPU family using the Curiosity Kit.
 

One promise of RISC-V is that it enables Architects, Systems Designers, and SW Developers to add custom instructions. However, if you don’t have your own CPU design team, how do you do this without breaking the RISC-V standard part of the pipeline? This talk will describe how the Andes Custom Extensions (ACE) enables simple and safe insertion of custom instructions while enabling software development and performance modeling.

In this presentation, we will unveil Tessent UltraSight-V, an end-to-end solution consisting of embedded IP and software designed to provide comprehensive, efficient debugging and trace capabilities that integrates with industry standard tool to further empower embedded software engineers in developing high-performance embedded software. The integration of Tessent UltraSight-V on-chip IP modules and host software empowers engineers to efficiently diagnose the root causes of unexpected behavior and underperformance. Utilizing effective, non-intrusive techniques such as encoded processor trace based on the Efficient Trace (E-trace) standard, logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads, this solution minimizes debugging delays and accelerates your SoC projects, ensuring they meet their market deadlines.

RISC-V cores can be found in more and more chips - as the main CPU(s) or as a companion core together with other CPU architectures. They can be implemented in subarchitectures like RISC-V RV32/RV64, AndesCore™ V5 or SiFive® Core IP. While the complexity of SoCs grows with the number of cores and the number of different core (sub)architectures, the challenges for embedded developers grow even more with operating systems, hypervisors, and other software running on multiple cores.

In this presentation, Lauterbach, market leader for development tools and strategic member of the RISC-V foundation, show how developers can overcome these challenges with the right tools and debug strategies. They explain how to debug cores from RISC-V and other architectures simultaneously via one debug interface and one debug probe to gain insight into the entire embedded system. The presentation covers real-time on- and off-chip tracing for all major RISC-V trace systems as well as the utilization of standardized RISC-V debug and trace interfaces.

Through this presentation the attendee learns that multicore debugging with RISC-V cores is not rocket science and that there are efficient methods to master even complex chips with complex software configurations.

This is a presentation introducing the RISC-V Processor IP company, which has recently come out of stealth mode. The presentation will go through the company, range of IP products available and benefits offered to customers.

The objective would be to present the Brazilian innovation ecosystem that operates in various business segments and the impact that RISC-V technology can bring to companies operating in these segments.