RISC-V Summit

ACPI for RISC-V has been under development since 3 years. It has now reached the state where every thing required to fully support ACPI on RISC-V server platforms is available. This talk will provide all the details about the specification changes and software support status for below key features required on server class platforms. 1) Hardware discovery 2) Power / performance management using LPI and CPPC 3) NUMA support 4) CPU-Cache topology information 5) IOMMU support 6) Reliability, Availability and Serviceability (RAS) support 7) Quality of Service Controller support. The talk will enlighten people that RISC-V ACPI ecosystem is ready for adoption.

Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks. This session will provide an overview of how the recently ratified Zicfiss and Zicfilp extensions help defend the programs control flow.

Since the Xuantie team promoted the integration of the RISC-V architecture within the AOSP mainline in 2022, the support for RISC-V in the Android system has become increasingly mature. This includes JIT/AOT modes support of Android Runtime, Cuttlefish emulator support, and optimization of numerous third-party libraries. Currently, the productization process of RISC-V Android is still in its early stages, with many upper-layer software stacks yet to achieve full compatibility with RISC-V. To further improve these software stacks, the Xuantie team, along with its partners, has explored productization in various customized scenarios such as payment, cloud desktops, and server clusters. This talk will share typical issues encountered during productization related to performance, stability, power consumption, and application compatibility; as well as how we addressed these issues.

Describe the software system to support CUDA running

The recently ratified RERI specification provides a open and standardized register interface specification for error reporting for RISC-V based designs targeting segments from HPC to embedded.

CHERI is an emerging security technology, jointly developed over the last decade by the University of Cambridge and SRI International. In this talk, we will describe the work being done to bring CHERI support to FreeBSD and Linux on RISC-V, where we can provide both memory safety as well as isolating software components to improve run-time safety, security and robustness.

RISC-V allows the freedom to innovate with custom instructions but working out which custom instructions add the most value is key to success and more easily done with simulation and models than RTL. At the same time new applications such as AI/ML are creating ever more complex SoCs with very high core counts. Using models in a digital twin of the design allows fast architectural exploration, accelerates software development and post silicon can help with DevOps flows and diagnosing in-field failures. This talk discusses two custom SoC projects where virtual platforms have been used to successfully develop software for many core systems in advance of silicon being available. This requires fast, accurate golden models of the CPUs in a simulation environment which can scale to hundreds or more cores.

This session provides an in-depth overview of a highly parameterizable open-source IOMMU IP compliant with the RISC-V IOMMU Specification v1.0. The IP was developed by Zero-Day Labs and is currently being verified in collaborative efforts with 10xEngineers. The presentation covers the implementation details of the IP, which includes features like two-stage address translation, MSI translation support, and internal IO Address Translation Caches (IOATCs) for improved performance. We discuss the verification process carried out in collaboration with 10xEngineers, which has achieved 85% of coverage targets and addressed several RTL bugs and design issues. Additionally, the session highlights the current applications of this IP in projects such as the AlSaqr 2.0 platform for autonomous nano-UAVs and the PULP Carfield architecture. The session concludes with future work plans (e.g., completing the verification and performing design optimizations) and opportunities for community collaboration to enhance the IP further.

Join us as we explore the journey of porting the SLEEF vectorized math library to the RISC-V architecture, focused on ensuring complete support for single, double, and quad precision math operations, Discrete Fourier Transforms (DFT), and testing all of it on QEMU on GitHub Actions.