RISC-V Summit

RISC-V's open standard provides a great opportunity to democratize the Domain Specific Processor market. Over the last twenty to thirty years, the processor market was dominated by general purpose closed-architectures. This environment limited processor engineering companies and job prospects. RISC-V enables a new going to market strategy that is not linked to a limited number of processor vendors, but a market strategy where the application and processor integrator defines and develops the Domain Specific Processor, the traditional System-On-Chip (SoC) developer. To extend custom processing to the larger segment of SoC developers, new processor engineers are required. Due to the lack of previous job prospects, there is a processor engineering shortage to sustain the pace of innovation. The RISC-V ecosystem is coming to the rescue. By developing processor Bounded Customization models where the Software Engineer uses standard software programming practices to architect and to develop custom processors, the inadequate supply of processor engineers can be solved. Who better than the application and algorithm engineer to become tomorrow's processor engineer.

The success of the RISC-V instruction set architecture depends on the ability for software to exploit the hardware effectively, both for the baseline (and now defined ISA profiles) and for new instruction set extensions. The LLVM compiler infrastructure (including Clang) is key for this, and has been a major success story for RISC-V software ecosystem enablement through cross-party collaboration. This talk provides an update on the current status, with up to date benchmarks for code size and generated code performance vs GCC. We'll explore how recent work in CI and tracking of these metrics has been helping to accelerate progress and ensure quality, and look ahead to future challenges.

A set of RISC-V Trace specifications developed by N-Trace TG has been recently ratified. It consists of three separated, but interconnected specifications: * RISC-V N-Trace (Nexus based) Trace Specification * RISC-V Trace Control Specification * RISC-V Trace Connectors Specification This session will explain key trace concepts and solutions. Relations to different existing trace standards will be highlighted. Practical use-cases, implementation hints and difficulties will be elaborated. Future development and possible enhancements will be mentioned.

In this talk, we will introduce the latest work we've done on matrix extension instructions (AME), the AI software stack for the first mass production RISC-V NPU card based on matrix, and the real commercial application cases in one 1000P computing center using large models. 1. As one of the first companies in the world to submit matrix extension proposals to the Foundation, we gained a lot of implementation experience on our first mass production NPU card STCP920, would like to share with audience about how we design and use some of instructions, as well as recent works in AME. 2. Based on STCP920, we completed a full software stack for AI application, will discuss some challages we encountered on LLVM, AI compiler and operators for example. 3. We just made a big win in one 1000P computing center project using NPU card, would like to share how to use RISC-V AI accelerator to build it, what's the strength and opportunities for RISC-V, what's the senario and application for AI. Generally speaking, we believe to provide computing power means to provide service.