Loading…
Attending this event?
October 22-23, 2024
Santa Clara, CA
View More Details & Registration

The Sched app allows you to build your schedule but is not a substitute for your event registration. You must be registered for RISC-V Summit to participate in the sessions. If you have not registered but would like to join us, please go to the event registration page to purchase a registration.
Mission City Ballroom B2 - B5 (Level 1) clear filter
arrow_back View All Dates
Tuesday, October 22
 

9:00am PDT

Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International
Tuesday October 22, 2024 9:00am - 9:20am PDT
Over the last decade, the industry standard RISC-V Instruction Set Architecture (ISA) has profoundly changed the computing industry with billions of cores shipped and a growing ecosystem of successful businesses all betting their future on RISC-V, but this is only just the beginning. In this session, Calista Redmond will discuss three ways that RISC-V is disrupting and defining the processor industry in the next decade. The ability to customize and extend RISC-V microprocessor designs will usher in an era of workload-defined silicon, where hardware / software co-design enables faster, more efficient compute, optimized for each application. This will power the deployment of AI in mainstream applications, where the flexibility to customize will accelerate innovation and adoption of AI worldwide. This new era of computing will enable developers, industries, and countries to solve local problems, together with access to a global ecosystem and market. Come and discover the future of computing!
Speakers
avatar for Calista Redmond

Calista Redmond

CEO, RISC-V International, RISC-V International
Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →
Tuesday October 22, 2024 9:00am - 9:20am PDT
Mission City Ballroom B2 - B5 (Level 1)

9:20am PDT

Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy
Tuesday October 22, 2024 9:20am - 9:35am PDT
The XuanTie team is dedicated to advancing RISC-V full-stack hardware and software technologies while fostering a robust ecosystem. Over the past year, we have partnered with industry leaders to deploy innovative RISC-V applications across a wide range of scenarios, from edge to cloud, like edge AI, 5G, laptops, servers, cloud infrastructure and more.

In this presentation, we will share XuanTie's efforts in advanced RISC-V development, including technical exploration in AI and high performance computing, as well how to achieve it by hardware and software co-development. Additionally, we will provide updates on XuanTie products and ecosystem build.
Speakers
avatar for Jing Yang

Jing Yang

VP of XuanTie, Alibaba DAMO Academy
Jing Yang received her Ph.D. and Master in EECS from UC Berkeley. She is currently the VP of XuanTie at Alibaba DAMO Academy. She is responsible for strategy, product, operation and sales. Her current job focuses on delivering high quality XuanTie products, collaborating internationally... Read More →
Tuesday October 22, 2024 9:20am - 9:35am PDT
Mission City Ballroom B2 - B5 (Level 1)

9:40am PDT

Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA
Tuesday October 22, 2024 9:40am - 10:00am PDT
Nine years ago, NVIDIA selected RISC-V for its embedded microcontrollers. Since then, we developed many processors and software stacks, all based on a common underlying hardware and software architecture. Today, every NVIDIA chip comes with multiple embedded RISC-V microcontrollers, each customized for a specific application. In the presentation, we will discuss our architecture as well as several applications. RISC-V’s rich feature set, configurability, extensibility, and active community are reasons why we stand by our 2015 decision to use RISC-V.
Speakers
avatar for Frans Sijstermans

Frans Sijstermans

Vice President Multimedia Arch/ASIC, NVIDIA
Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia... Read More →
Tuesday October 22, 2024 9:40am - 10:00am PDT
Mission City Ballroom B2 - B5 (Level 1)

10:00am PDT

Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology
Tuesday October 22, 2024 10:00am - 10:15am PDT
As an open standard, RISC-V architecture has been fast adopted in many major embedded applications, including AI/ML for Cloud and Edge, Automotive, 5G/Networking, MCU/MPU, Multimedia, Storage, Sensor Processing, and Wireless Connectivity. It also started showing up on initial systems of personal computing devices as well as servers. All those applications will continue to be key drivers for global semiconductor industry at least for the next several years and create further opportunity for RISC-V to grow its market share.
 
In this talk, we will look at RISC-V’s successful stories in various applications. Then we will share our insight of some RISC-V features and ecosystem important for several key technologies behind those applications. We will cover AI/ML acceleration, application processing, embedded and real-time systems, functional safety and security. We will use Andes products as examples for illustration’s purpose.
Speakers
avatar for Dr. Charlie Su

Dr. Charlie Su

President and CTO, Andes Technology
Dr. Charlie Su, Co-founder, CTO and President of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member... Read More →
Tuesday October 22, 2024 10:00am - 10:15am PDT
Mission City Ballroom B2 - B5 (Level 1)

10:15am PDT

Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys
Tuesday October 22, 2024 10:15am - 10:25am PDT
Vehicles are undergoing a period of massive evolution driven by increased levels of autonomy, new in-car experiences, and electrification, driving the automotive supply chain to deliver greater innovation while streamlining the product life cycle. RISC-V is the Open Standard Instruction Set Architecture (ISA) that uniquely scales across every in-vehicle compute application, cost effectively delivering innovation opportunities to meet diverse compute requirements that power future generations of vehicles. This session explores how the RISC-V ISA can be used to simplify development and deployment of extensible, power- and area-efficient hardware and software innovation across vehicle ranges and models. It will discuss how RISC-V implementations and ecosystem can offer efficiencies for the automotive supply chain, and the new possibilities it will open up for in-vehicle compute experiences.
Speakers
avatar for Rich Collins

Rich Collins

Sr. Director Product Management - ARC Processors, Synopsys
Tuesday October 22, 2024 10:15am - 10:25am PDT
Mission City Ballroom B2 - B5 (Level 1)

10:30am PDT

Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology
Tuesday October 22, 2024 10:30am - 10:45am PDT
As embedded computing evolves, scalable, high-performance solutions are essential. In this keynote, Mr. Patrick Johnson, Senior Vice President, FPGA and Timing Business Units at Microchip Technology, Inc. will explore the capabilities of Microchip's new 64-bit PIC64 microprocessors. Attendees will learn how these processors handle complex workloads across industrial, automotive, aerospace, and defense sectors.

Discover the unique architecture of the PIC64GX, featuring high-performance RISC-V cores, advanced memory management, and flexible interconnects designed for intelligent edge applications. Key highlights include:

- Enhanced performance, reduced latency, and improved system reliability
- Real-world use cases showcasing the capabilities of PIC64 microprocessors
- Microchip’s MPLAB extension for unified development across multiple ISAs

Gain insights into designing high-performance embedded systems with Microchip's innovative solutions. Join us to explore the future of intelligent edge computing.
Speakers
avatar for Patrick Johnson

Patrick Johnson

Sr. Corporate Vice President, Microchip Technology
Patrick Johnson serves as Senior Corporate Vice President at Microchip, where he oversees thecompany's FPGA, Security, Timing, and Touch Screen product lines. Additionally, he acts as theexecutive sponsor for the Aerospace & Defense business segment. Prior to this role, Johnsonwas... Read More →
Tuesday October 22, 2024 10:30am - 10:45am PDT
Mission City Ballroom B2 - B5 (Level 1)

4:15pm PDT

Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework
Tuesday October 22, 2024 4:15pm - 4:30pm PDT
The RISC-V ISA is one of the most exciting recent developments in computing with amazing potential to revolutionise applications and industries worldwide. But what does it take to bring consumer products to market based on this young ISA? This session will explore how DeepComputing and their partners worked together to develop a range of products including the first RISC-V based laptop and tablet. It will detail the risk taking, collaboration, learning and accelerated technical development needed to put these products into the hands of consumers worldwide. Come and be inspired, maybe next year’s biggest RISC-V based product could be designed by you.
Speakers
avatar for Nirav Patel

Nirav Patel

Founder and CEO, Framework
Nirav Patel is the Founder and CEO of Framework, makers of the Framework Laptop.
avatar for Yuning Liang

Yuning Liang

CEO, DeepComputing
Yuning is the founder and CEO of Xcalibyte and Advisor of DeepComputing which makes RISC-V SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.Yuning’s career took him from UK to Switzerland to South Korea and finally to China. He comes... Read More →
Tuesday October 22, 2024 4:15pm - 4:30pm PDT
Mission City Ballroom B2 - B5 (Level 1)

4:30pm PDT

Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley
Tuesday October 22, 2024 4:30pm - 4:45pm PDT
10 years ago, David Patterson and Krste Asanović made the case for RISC-V as an open Instruction Set Architecture with the vision that it become the standard ISA for all computing devices. In this session, David Patterson revisits the arguments we made in that paper and the objections to it at the time then gives his views of the progress made in the subsequent decade and his thoughts on the future. 
Speakers
avatar for David Patterson

David Patterson

Pardee Professor of Computer Science, Emeritus, University of California at Berkeley
David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976.Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of... Read More →
Tuesday October 22, 2024 4:30pm - 4:45pm PDT
Mission City Ballroom B2 - B5 (Level 1)

4:50pm PDT

Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted Speers, Microchip; Calista Redmond, RISC-V
Tuesday October 22, 2024 4:50pm - 5:30pm PDT
The impact of computing on our modern world is profound, changing our daily life with new ways to communicate, work, and play. Until now, advances in computing have been led by a limited number of companies and countries. RISC-V has changed everything and taken down the barriers to entry. As the industry standard ISA, RISC-V has opened doors for companies big and small, universities and research institutes, and even governments to engage in the global digital economy. RISC-V enables engineers and developers worldwide to innovate locally, with access to a global ecosystem and market. In this panel, we gather experts from around the world to discuss how RISC-V is changing computing in their geography through direct investments, collborations, and incentives to build a bright digital future.

Moderators
avatar for Calista Redmond

Calista Redmond

CEO, RISC-V International, RISC-V International
Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →
Speakers
avatar for Alessandro Campos

Alessandro Campos

General Coordinator of Semiconductor, Ministry of Science, Technology, Innovations
Alessandro Augusto Nunes Campos, Doctor in Science in Electrical Engineering - Semicon, Bachelor in Computer Engineering and Civil Engineering, worked in research in Aerospace, Information and Communication Technology (ICT), Semiconductors and Engineering. He has taught at renowned... Read More →
avatar for Jianying Peng

Jianying Peng

Co-founder and CEO, Nuclei System Technology
Dr Jianying Peng, graduated from School of Micro-Nano Electronics, Zhejiang University, has more than 15 years of CPU processor design and management experience. Previously Dr Peng worked in Marvell and Synopsys where she led multiple high performance processor designs in ARM and... Read More →
avatar for Roger Espasa

Roger Espasa

CEO & Founder, Semidynamics
Roger Espasa is the founder and CEO of Semidynamics, a European IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected... Read More →
avatar for Ted Speers

Ted Speers

Technical Fellow, Microchip
Tuesday October 22, 2024 4:50pm - 5:30pm PDT
Mission City Ballroom B2 - B5 (Level 1)
 
Share Modal

Share this link via

Or copy link

Filter sessions
Apply filters to sessions.
Filtered by Date -