RISC-V Summit

The automotive industry is experiencing a massive paradigm shift. Cars are becoming increasingly autonomous, connected, and computerized. Modern E/E-architectures are pushing for an unforeseen functionality integration density, resulting in physically separate ECUs becoming virtualized and mapped to logical partitions within a single physical MCU. While functional safety has been pivotal for vehicle certification for decades, this increasing connectivity have shed light on the need for (cyber-)security and paved the way for the release of the new standard ISO21434. RISC-V has a pivotal opportunity to transform automotive computing systems, but we argue that current ISA / extensions are not ready yet. This talk provides our critical perspective on the existing limitations, particularly the upcoming WorldGuard technology, to address virtualized MCU requirements per foreseen automotive applications. We then present our proposal to address such limitations, mainly targeting master-side protection. We complete the talk by explaining the roadmap towards a full open-source Proof-of-Concept, which includes extending QEMU, an open-source RISC-V Core, and building a complete software stack.

In embedded system development, several technical issues need to be solved to facilitate the transition from another architecture to RISC-V. For example, in existing embedded devices, there are products with multiple OSs, including RTOS. In such products, hardware virtualization is used to run General Purpose OS(GPOS) and RTOS to guarantee real-time performance and use GPOS software assets. However, some OSs (especially RTOS) are not intended to run on virtual machines. Therefore, we are researching a mechanism that enables all RTOSs to run even on a RISC-V virtual machine. In this talk, we will provide strategies for running the RTOS on virtual machines and the issues to be solved for its practical use.

In last year’s North America Summit, Dr. Jianying Peng presented Nuclei’s NA900 (automotive) RISC-V core as the world’s 1st ASIL-D product certified RISC-V core in the automotive session. For the past 1 year, Nuclei has continued to develop functional safety solution including world’s 2nd ASIL-D product certified RISC-V core NA300 and bus fabric with safety features. Nuclei has extended the scope to information security as well. Beyond RISC-V core and bus fabric, Nuclei has released HSM (hardware security module) based on RISC-V core recently. By doing this, the position of RISC-V in the automotive ecosystem has been further strengthened with a comprehensive set of combined RISC-V based security & functional safety solutions. Thus this year we would like to share 4 topics from technical, ecosystem and business perspectives: 1. Nuclei’s experience in functional safety and security design 2. Nuclei’s experience in automotive SoC design 3. Automotive electronics software ecosystem 4. Customer success stories and open concern of RISC-V from different customers we see in the past 2 years.

Ensuring security in Central Processing Units (CPUs) has become a critical concern. This presentation examines the importance of CPU security in the context of RISC-V , with a focus on addressing potential vulnerabilities through various security measures. In the presentation we explore and analyze different types of cyber-attacks relevant to RISC-V CPUs, such as code injection, buffer overflows and jump-orienting programming but also cyber-physical attacks like side-channel attacks, fault injections, and supply chain attacks such as hardware Trojans. We discuss the concept of Lockstep as a redundancy technique and Code & Control-Flow Integrity verification (CCFI) to enhance security and safety by detecting and correcting errors or malicious manipulations. Additionally, the presentation emphasizes the significance of industry-standard certifications (Common Criteria, FIPS 140-3) in verifying the effectiveness of security solutions. Finally, we explain why, by understanding and implementing robust security measures, RISC-V CPUs can establish a strong foundation for secure computing environments, safeguarding against diverse cyber threats and risks.

I would like to introduce our success story of adopting RISC-V CPU in the embedded domain with the ability to customize the architecture. For this success, we developed a scalable, orthogonal and transparent interrupt architecture which enabled the control of extremely timing-critical tasks. I believe this architecture can be widely adopted across multiple domains with the configurability to adopt to their own requirements.

Berberis is an open source userspace dynamic binary translator facilitating cross-architecture development and testing of RISC-V Android applications. It translates native riscv64 code inside of an Android APK to x86_64 at runtime, enabling developers to test RISC-V builds of their apps on their workstations when target device hardware is unavailable. This presentation will cover the motivation and benefits of userspace translation versus whole-system emulation, the challenges of translating RISC-V code to x86_64, and use cases and future directions for the project.

Mission Critical Edge Compute demands high-performance MPUs with time and space partitioning capabilities to enable mixed-criticality workloads. As well, the MPUs must be built with comprehensive fault-tolerance and fault-isolation capabilities. Given these requirements, A&D and Industrial systems developers worldwide are looking to RISC-V as a key enabling technology to enable their next-generation platforms. This presentation will explore: 1) Why RISC-V for Mission Critical Edge Compute: Virtualization, Vector Processing, and WorldGuard Partitioning 2) How RISC-V is set to transform space computing 3) The opportunities for RISC-V in aviation 4) Applications for RISC-V in industrial applications This presentation will conclude with how Microchip is responding and a call-to-action for what is needed from the RISC-V ecosystem to fully capitalize on this once in a generation opportunity to transform critical infrastructure.

Version 1.0.0 of the RISC-V Vector Cryptography extensions specification was ratified in late 2023 and adds high-performance cryptography operations to the comprehensive list of ISA features that RISC-V officially supports. We present the first open-source implementation of the RISC-V Vector Cryptography specification, using the PULP Project's Ara vector processor as a baseline and targeting a 28nm technology node. We present the design/verification opportunities and challenges that were encountered. Furthermore, a detailed review of the implementation and benchmarking results will be included in the presentation.