strong>Expo Hall - Exhibit Hall A (Level 1) [
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3:35pm PDT
HPC & Data Center Poster Sessions
Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Speakers
Principal Engineer, Tenstorrent Inc.
Sajosh has over 20 years of experience in the semiconductor industry, participating in various stages of chip design, from microarchitecture development to post-silicon debug. Currently at Tenstorrent, he is working on RISC-V CPUs and AI SoCs that scale to meet different PPA (Power/Performance/Area...
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3:35pm PDT
ISA & Design Tools Poster Sessions
Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Speakers
Technical Community Architect, RISC-V International
Senior documentation Architect, RISC-V International
I enjoy reading, baking, canning, pets, hiking, national parks, and most of all, documentation!
M.A.Sc Student, University of British Columbia
Sr. Architect, R&D, Synopsys
Eino Jacobs has decades of experience with architecture and design of high-performance processors. He works now on RISC-V Vector processors. He is also a lead architect and designer of the VPX and ARC processor product lines at Synopsys.
Principal Engineer, Tenstorrent Inc.
Darshak Koshiya is a Principal Engineer at Tenstorrent, involved in design of hardware to accelerate AI workloads and high performance CPU. He is currently involved with the core verification of RISC-V high performance CPU design.Prior to joining Tenstorrent, Darshak was a Senior...
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PhD Student, The University of Manchester
John Alistair Kressel is a PhD student and research assistant in the Advanced Processor Technology (APT) group at the University of Manchester. He recently completed his MPhil researching software compartmentalization using CHERI hardware capabilities. His interests include software...
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Professor, University of British Columbia
Guy is a Professor in Computer Engineering at the University of British Columbia where he teaches digital design and computer systems/architecture courses. His research focuses on improving FPGA devices and CAD tools, in particular making them easier to use and more efficient for...
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Professor, University of Manchester
Mikel Luján received the PhD degree in computer science from The University of Manchester, U.K., in 2002. He is currently a professor with the Department of Computer Science, The University of Manchester, where he holds the Royal Academy of Engineering Research Chair on Computer...
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Professor, University of Cambridge
Staff Engineer, Tenstorrent
Pravin Tavagad is currently working as CPU DV Staff engineer at Tenstorrent Bangalore.His areas of interests are CPU, Memory subsystem and SoC Design verification.Prior to joining tenstorrent he has worked on various architectures like x86_64, ARM, Tensilica xtensa.
Sr. Architect Sw Engineering, Synopsys
Dmitry Utyanskiy has been involved in embedded software development and Digital Signal Processing algorithms design, optimization and application for communications, RADAR, audio and image processing since his graduation from St. Petersburg Electrotechnical University in 1994. Currently...
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RISC V Intern, Tenstorrent
B Midhun Varman has been part of Tenstorrent for the past one year .In his current role, he is responsible for Verification of High-Performance RISC-V cores specifically in the JTAG module and building various cluster level tests. He holds a B.Tech and M.tech in Electrical Engineering...
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3:35pm PDT
Security Poster Sessions
Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Speakers
Distinguished Engineer and Lead IP Architect, Codasip
I have been chair of RISC-V code-size, and Zfinx, and these days am heavily involved in CHERI standardisation for RISC-V.
Founding Director of the CHERI Alliance, CHERI Alliance
Mike Eftimakis has an extensive background in the electronics industry with 30 years in senior technical and business roles. He has been innovating with companies like VLSI Technology, NewLogic or Arm.He is now VP Strategy and Ecosystem at Codasip, where he drives the long-term vision...
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Research Associate, University of Cambridge
Peter Rugg is a Research Associate in hardware security at the University of Cambridge. Since completing his PhD in 2023, he has continued his research on extending processors with architectural security features, with a focus on efficient, deterministic protection. Particular areas...
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