RISC-V Summit

Implementing and Verifying RISC-V Nexus Trace Compliant Trace Encoder for High Performance Cores - Sajosh Janarthanam, Tenstorrent Inc.
In this poster, we present the N-trace infrastructure, which supports instruction tracing for multiple out-of-order RISC-V cores. We discuss the architectural and microarchitectural decisions involved in designing the Encoder. Furthermore, we describe the infrastructure established to facilitate efficient trace transmission. Finally, we discuss the strategies employed to verify the Encoder and its associated components.

RISC-V "V" Vector Extension (RVV) with Reduced Number of Vector Registers - Eino Jacobs & Dmitry Utyanski, Synopsys
Reduce the number of vector registers to reduce the area of small processors for DSP applications.

MAMBO: Dynamic Binary Modification on RISC-V - John Kressel & Mikel Lujan, University of Manchester
Dynamic Binary Modification (DBM) is an important technique used in computer architecture simulators, virtualization, and program analysis, to name a few examples. The software ecosystem of RISC-V is maturing at pace, but is still missing a high-performance, optimized DBM. Addressing this requirement is key to improving the overall software ecosystem. This paper presents a comprehensive performance evaluation study for a DBM (MAMBO) which has been ported and optimized for 64-bit RISC-V. The main optimizations for DBM on RISC architectures have been implemented and tuned for RISC-V to address specific architectural features. For example, jump trampolines have been specifically developed to address the short direct branch range specified by the RISC-V ISA. The evaluation shows that for SPEC CPU2006 the geometric mean overhead is of 14.5%, with SPECint having the largest contribution with a geometric mean of 28.5%, while SPECfp has only an overhead of 5.6%. Concretely, this results in a reduction in runtime for h264ref from over 75 hours using the baseline DBM, to 2.2 hours with optimizations applied.

TestRIG - Professor Simon Moore, University of Cambridge
TestRIG is a framework for directed randomized testing of RISC-V cores. It leverages the QuickCheck automatic testing library and the RISC-V sail model to find potential trace divergences and report minimal instruction sequences triggering a bug in an implementation, helping with RTL bring-up and debugging.

MXM-RVV: Easy Multicore X Multithreading with Vectors via Composable Extensions + DMA - Joseph Maheshe, Guy Lemieux & Brandon Freiberger, University of British Columbia
We revisit the topic of multithreaded vector processors, but now within the RISC-V architecture. By combining data-level and thread-level parallelism, we further improve performance. We create an SoC with one hart and multiple RVV vector units, where each vector unit contains multiple contexts (multithreading), using the Draft CX Specification. We add an independent instruction queue to each context within each vector unit, thereby enabling asynchronous multicore, multithreaded execution of vector instructions with a single scalar thread and hardware scheduling of the parallel queues.
To make this work, we show that non-blocking vector loads and stores are essential to hide memory latency by executing instructions from other contexts. We use a round-robin scheduling scheme for fine-grained multithreading. We illustrate how to write software to target the MXM-RVV and show that it requires minimal changes.

Open-Source Self-Checking RISC-V Architectural Tests - Darshak Koshiya, Tenstorrent Inc.
This presentation introduces a collection of self-checking RISC-V Instruction Set Architecture (ISA) directed tests designed to help streamline the verification process for RISC-V designs. These tests leverage an end-of-test mechanism, that eliminates the need for pre-defined expected outputs and simplifies test execution. These open-source tests employ randomly generated operands and data avoiding the pitfalls of the using simple constants.This presentation will delve into the design and implementation details of these pen-source tests, showcasing their effectiveness in the verification of RISC-V ISA implementations and facilitating a more streamlined verification process for RISC-V cores. 

Emulation-Friendly, Efficient, Self-Checking  RISC-V Compliant JTAG-DFD Testbench Mechanism - Pravin Tavagad & Midhun Varman, Tenstorrent
The increasing complexity of modern electronic systems and RISC-V based SoC designs demands robust testing methodologies to ensure reliability and performance. JTAG testbenches have become essential tools for debugging and verifying integrated circuits. However, traditional JTAG testbenches often face challenges in terms of emulation friendliness, efficiency, quick turn around time, reusability and scalability. We present an approach that addresses the critical need for an advanced JTAG testbench for complex RISC-V based designs that overcomes these limitations. Additionally, our approach supports access to various RISC-V components such as the RISC-V Debug module via the RISC-V Debug Transport Module (DTM), the RISC-V compliant Trace module

Simplifying Sail and Architecture Compatibility Testing Setups with Containers - Greg Sterling, RISC-V International

RISC-V Documentation Guidelines: Is it 'Which' or 'That'? - Kersten Richter & Bill Traynor, RISC-V International

Commercializing CHERI on a Codasip A730 RISC-V Application Core - Tariq Kurd, Codasip
Memory safety continues to cause widespread and costly cyber security problems. Data breaches often arise from memory safety vulnerabilities leading to multi-million dollar losses for victims; for example, losses due to the well-known OpenSSL Heartbleed bug are estimated to exceed $500 million. Therefore, there is increasing interest in the Capability Hardware Enhanced RISC Instructions (CHERI) which is an ISA extension that mitigates memory safety vulnerabilities by design. CHERI has been primarily a research project until now! The University of Cambridge, which originated the technology, partnered with Codasip to propose a CHERI extension for RISC-V. Codasip also unveiled the first commercial implementation of a CHERI RISC-V: the A730 processor. In this poster, we introduce the A730 processor microarchitecture and highlight the main challenges to supporting CHERI RISC-V. We also describe the key differences between A730 implementations with and without CHERI support. In our experience, the A730 with CHERI is about 4% larger in area than an A730 without CHERI.

CHERI RISC-V Standardization - Peter Rugg, University of Cambridge
CHERI is a cross-architecture security technology, adding memory safety and compartmentalization features via capability support in the hardware. This poster will present the current effort to standardize the architectural extensions required to obtain these benefits in RISC-V: currently an effort shared by University of Cambridge, Codasip, Google, and others. The standardization work has been proceeding at pace, with a concrete specification document available, and extensive community interaction to iron out edge cases and ensure applicability to a wide range of uses.

The CHERI Alliance – Getting the Industry Together to Tackle a $10T / Year Problem - Mike Eftimakis, CHERI Alliance
Cybercrime costs the World more than $10T / year, and this amount is growing at an alarming rate. A study of software vulnerabilities has shown that over the past 20 years, memory attacks represented more than 70% of them. CHERI technology has been developed to solve the problem and has been proven to work. After 14 years of research and prototyping, CHERI is now ready to get out of the lab! A new CHERI SIG has been formed in RISC-V International, but adoption won’t happen without a significant industry-led effort: this is the goal of the CHERI Alliance.