RISC-V Summit

In this presentation, we will share the latest progress in the XuanTie IP products and software stack. We invite you join to discuss the latest developments in RISC-V.

Vehicles are rapidly evolving to become electrified, connected, more software-defined, and increasingly autonomous. This transformation presents a significant opportunity for open-standard RISC-V processors in automotive electronic systems, offering tailored optimization for various applications, from sensor processing and ECUs to domain, zonal, and central compute units. As the complexity of these systems continues to grow exponentially, it is crucial that the solutions adhere to rigorous standards like ISO 26262. This talk will explore these essential standards and showcase how Andes' cutting-edge solutions are designed to meet the highest levels of safety in the automotive industry.

CHERI is a fine-grained memory protection technology that protects your system against buffer overflows and other memory safety issues. CHERI is implemented in hardware and enabled by supporting software. This demo simulates a real buffer overflow attack on an application running a full OS. We will show how a Codasip application core with CHERI enabled can identify the attack and stop the system without any secrets being accessed.

In this presentation, we will provide an overview of Ashling’s TraceLLM which offers unprecedented insights into your program’s real-time behavior through an intelligent trace capture and AI LLM based analysis software engine which can be queried using a natural language, prompt-based interface. TraceLLM, which works with the Ashling Vitra-XS hardware trace probe and RiscFree software debugger has the capability to understand the entire program execution flow and can answer any questions related to the program execution in a natural language and provide quick and accurate responses, substantially bringing down the time spent by developers for debugging. Dive into your program's behavior and watch as the intelligent engine examines the captured trace and delivers unprecedented insights including pinpointing potential bottlenecks, performance issues and offering actionable insights. Enhance efficiency, accelerate problem solving, and harness the full potential of your RISC-V systems with Ashling’s TraceLLM today.

As RISC-V adoption grows, how are EDA tools and IP adapting to address new and evolving design challenges? From architecture exploration to design implementation and software development, SoC designers are looking for ways to take advantage of the RISC-V ecosystem and deliver optimized products with fast time-to-market.  At Synopsys, we’re building RISC-V solutions to help customers from the beginning of the project to delivery and deployment, supporting the full RISC-V ISA plus custom instructions while enabling architecting of workload-optimized processors, comprehensive processor verification, and pre-silicon software development. Whether you are building your own RISC-V core, using a partner’s core, or implementing Synopsys ARC-V processor IP,  Synopsys can help you meet your project requirements.  This presentation will provide an overview of the broad range of Synopsys RISC-V solutions that have been proven by our customers taking RISC-V SoCs to silicon.

In this talk we will cover the latest developments in running modern transformers , such as LLama-2, on Semidynamics RISC-V "All-In-One" solution, comprising a core, a Vector Unit and a Tensor Unit. In this talk you'll learn about how ONNX RT is used to deploy modern models on Semidynamics solution, on how the ratio of the vector to tensor compute is important for balanced execution and how the all-in-one can be scaled-out to reach different performance
levels.

In this session, Canonical will introduce the work being done by the organization to optimize Ubuntu, the most popular Linux operating system, for RISC-V. We will present the Canonical roadmap and vision for Ubuntu on RISC-V, this will include: 

• Ubuntu and Canonical roadmap for RISC-V profiles 
  
• How to enable vendor differentiation and make the unique vendor IP shine in Ubuntu 
  
• We will present the depth of our partnerships and contributions towards open source and community projects via RISC-V International and RISE 
  

In an era defined by rapid technological advancement, the intersection of semiconductor process innovation and artificial intelligence is reshaping industries and driving new paradigms of computing. This talk explores the key market trends, growth forecast and factors driving new use cases.  We will also share how Samsung Foundry is enabling customer innovations in particular around RISC-V where chip and chiplet performance optimization resulting in smarter and more efficient systems.  By examining current trends and future prospects, we aim to illuminate the path forward for engineers, developers, and decision-makers in harnessing the power of silicon technologies, advanced packaging, RISC-V and AI to create cutting-edge solutions that meet the demands of a rapidly evolving digital landscape.