RISC-V Summit

Ensuring security in Central Processing Units (CPUs) has become a critical concern. This presentation examines the importance of CPU security in the context of RISC-V , with a focus on addressing potential vulnerabilities through various security measures. In the presentation we explore and analyze different types of cyber-attacks relevant to RISC-V CPUs, such as code injection, buffer overflows and jump-orienting programming but also cyber-physical attacks like side-channel attacks, fault injections, and supply chain attacks such as hardware Trojans. We discuss the concept of Lockstep as a redundancy technique and Code & Control-Flow Integrity verification (CCFI) to enhance security and safety by detecting and correcting errors or malicious manipulations. Additionally, the presentation emphasizes the significance of industry-standard certifications (Common Criteria, FIPS 140-3) in verifying the effectiveness of security solutions. Finally, we explain why, by understanding and implementing robust security measures, RISC-V CPUs can establish a strong foundation for secure computing environments, safeguarding against diverse cyber threats and risks.

This deep dive will explain an end to end software stack solution to RISC-V based AI chips, including an innovation way to write AI kernels with new programming languages such as Triton (and Mojo later), using MLIR/LLVM based AI compiler infra to lower Triton kernels and neural networks from frameworks such as Pytorch, ONNX, Tensorflow and JAX into a range of high/middle/low level of MLIR dialects to do coarse grained high level optimizations such as loop tiling, kernel fusion, auto-vectorization etc. This paves the way of sharing common open source Triton kernels libraries provided in PyTorch and other frameworks, and greatly reduces the adoption time for AI software stack to RISC-V based AI chip. This talk will also explore the limitation of Triton language, and how can we extend the Triton language, and also the MLIR conversion and optimization passes to better support non GPU architecture target such as RISC-V.