RISC-V Summit: Full Schedule

October 22-23, 2024
Santa Clara, CA
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8:00am PDT

Registration & Badge Pick-up

Tuesday October 22, 2024 8:00am - 7:00pm PDT

Main Lobby (Level 1)

Tuesday October 22, 2024 8:00am - 7:00pm PDT
Main Lobby (Level 1)

Special Events / Exhibits / Breaks

9:00am PDT

Keynote: The Next Computing Megatrends are Enabled by RISC-V - Calista Redmond, CEO, RISC-V International

Tuesday October 22, 2024 9:00am - 9:20am PDT

Mission City Ballroom B2 - B5 (Level 1)

Over the last decade, the industry standard RISC-V Instruction Set Architecture (ISA) has profoundly changed the computing industry with billions of cores shipped and a growing ecosystem of successful businesses all betting their future on RISC-V, but this is only just the beginning. In this session, Calista Redmond will discuss three ways that RISC-V is disrupting and defining the processor industry in the next decade. The ability to customize and extend RISC-V microprocessor designs will usher in an era of workload-defined silicon, where hardware / software co-design enables faster, more efficient compute, optimized for each application. This will power the deployment of AI in mainstream applications, where the flexibility to customize will accelerate innovation and adoption of AI worldwide. This new era of computing will enable developers, industries, and countries to solve local problems, together with access to a global ecosystem and market. Come and discover the future of computing!

Speakers

Calista Redmond

CEO, RISC-V International, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Tuesday October 22, 2024 9:00am - 9:20am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:20am PDT

Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success - Jing Yang, VP of XuanTie, Alibaba DAMO Academy

Tuesday October 22, 2024 9:20am - 9:35am PDT

Mission City Ballroom B2 - B5 (Level 1)

The XuanTie team is dedicated to advancing RISC-V full-stack hardware and software technologies while fostering a robust ecosystem. Over the past year, we have partnered with industry leaders to deploy innovative RISC-V applications across a wide range of scenarios, from edge to cloud, like edge AI, 5G, laptops, servers, cloud infrastructure and more.

In this presentation, we will share XuanTie's efforts in advanced RISC-V development, including technical exploration in AI and high performance computing, as well how to achieve it by hardware and software co-development. Additionally, we will provide updates on XuanTie products and ecosystem build.

Speakers

Jing Yang

VP of XuanTie, Alibaba DAMO Academy

Jing Yang received her Ph.D. and Master in EECS from UC Berkeley. She is currently the VP of XuanTie at Alibaba DAMO Academy. She is responsible for strategy, product, operation and sales. Her current job focuses on delivering high quality XuanTie products, collaborating internationally... Read More →

Tuesday October 22, 2024 9:20am - 9:35am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

9:40am PDT

Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billons of Processors - Frans Sijstermans, Vice President Multimedia Arch/ASIC, NVIDIA

Tuesday October 22, 2024 9:40am - 10:00am PDT

Mission City Ballroom B2 - B5 (Level 1)

Nine years ago, NVIDIA selected RISC-V for its embedded microcontrollers. Since then, we developed many processors and software stacks, all based on a common underlying hardware and software architecture. Today, every NVIDIA chip comes with multiple embedded RISC-V microcontrollers, each customized for a specific application. In the presentation, we will discuss our architecture as well as several applications. RISC-V’s rich feature set, configurability, extensibility, and active community are reasons why we stand by our 2015 decision to use RISC-V.

Speakers

Frans Sijstermans

Vice President Multimedia Arch/ASIC, NVIDIA

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia... Read More →

Tuesday October 22, 2024 9:40am - 10:00am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:00am PDT

Keynote: Leveraging RISC-V for All Computing Devices - Dr. Charlie Su, President and CTO, Andes Technology

Tuesday October 22, 2024 10:00am - 10:15am PDT

Mission City Ballroom B2 - B5 (Level 1)

As an open standard, RISC-V architecture has been fast adopted in many major embedded applications, including AI/ML for Cloud and Edge, Automotive, 5G/Networking, MCU/MPU, Multimedia, Storage, Sensor Processing, and Wireless Connectivity. It also started showing up on initial systems of personal computing devices as well as servers. All those applications will continue to be key drivers for global semiconductor industry at least for the next several years and create further opportunity for RISC-V to grow its market share.

In this talk, we will look at RISC-V’s successful stories in various applications. Then we will share our insight of some RISC-V features and ecosystem important for several key technologies behind those applications. We will cover AI/ML acceleration, application processing, embedded and real-time systems, functional safety and security. We will use Andes products as examples for illustration’s purpose.

Speakers

Dr. Charlie Su

President and CTO, Andes Technology

Dr. Charlie Su, Co-founder, CTO and President of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member... Read More →

Tuesday October 22, 2024 10:00am - 10:15am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:15am PDT

Keynote: Shaping the Future of Automotive Computing with RISC-V - Rich Collins, Sr. Director Product Management - ARC Processors, Synopsys

Tuesday October 22, 2024 10:15am - 10:25am PDT

Mission City Ballroom B2 - B5 (Level 1)

Vehicles are undergoing a period of massive evolution driven by increased levels of autonomy, new in-car experiences, and electrification, driving the automotive supply chain to deliver greater innovation while streamlining the product life cycle. RISC-V is the Open Standard Instruction Set Architecture (ISA) that uniquely scales across every in-vehicle compute application, cost effectively delivering innovation opportunities to meet diverse compute requirements that power future generations of vehicles. This session explores how the RISC-V ISA can be used to simplify development and deployment of extensible, power- and area-efficient hardware and software innovation across vehicle ranges and models. It will discuss how RISC-V implementations and ecosystem can offer efficiencies for the automotive supply chain, and the new possibilities it will open up for in-vehicle compute experiences.

Speakers

Rich Collins

Sr. Director Product Management - ARC Processors, Synopsys

Tuesday October 22, 2024 10:15am - 10:25am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:30am PDT

Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions - Patrick Johnson, Sr. Corporate Vice President, Microchip Technology

Tuesday October 22, 2024 10:30am - 10:45am PDT

Mission City Ballroom B2 - B5 (Level 1)

As embedded computing evolves, scalable, high-performance solutions are essential. In this keynote, Mr. Patrick Johnson, Senior Vice President, FPGA and Timing Business Units at Microchip Technology, Inc. will explore the capabilities of Microchip's new 64-bit PIC64 microprocessors. Attendees will learn how these processors handle complex workloads across industrial, automotive, aerospace, and defense sectors.

Discover the unique architecture of the PIC64GX, featuring high-performance RISC-V cores, advanced memory management, and flexible interconnects designed for intelligent edge applications. Key highlights include:

- Enhanced performance, reduced latency, and improved system reliability
- Real-world use cases showcasing the capabilities of PIC64 microprocessors
- Microchip’s MPLAB extension for unified development across multiple ISAs

Gain insights into designing high-performance embedded systems with Microchip's innovative solutions. Join us to explore the future of intelligent edge computing.

Speakers

Patrick Johnson

Sr. Corporate Vice President, Microchip Technology

Patrick Johnson serves as Senior Corporate Vice President at Microchip, where he oversees thecompany's FPGA, Security, Timing, and Touch Screen product lines. Additionally, he acts as theexecutive sponsor for the Aerospace & Defense business segment. Prior to this role, Johnsonwas... Read More →

Tuesday October 22, 2024 10:30am - 10:45am PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

10:45am PDT

Coffee Break

Tuesday October 22, 2024 10:45am - 11:30am PDT

Exhibit Hall A

Tuesday October 22, 2024 10:45am - 11:30am PDT
Exhibit Hall A

Special Events / Exhibits / Breaks

10:45am PDT

Expo Hall

Tuesday October 22, 2024 10:45am - 7:00pm PDT

Exhibit Hall A

Tuesday October 22, 2024 10:45am - 7:00pm PDT
Exhibit Hall A

Special Events / Exhibits / Breaks

10:50am PDT

Demo: XuanTie RISC-V Hardware and Software Full-stack Technology - James Shi, Alibaba DAMO Academy

Tuesday October 22, 2024 10:50am - 11:10am PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this presentation, we will share the latest progress in the XuanTie IP products and software stack. We invite you join to discuss the latest developments in RISC-V.

Speakers

James Shi

Alibaba DAMO Technology Co., Ltd.

I am James Shi. I am currently a principal STE at Alibaba Damo academy, my current main focusing is on kernel & Linux OS testing for Xuantie RISC-V processors.Some of my work is also related wtih validating CPU memory models, system integration testing and performance testing for... Read More →

Tuesday October 22, 2024 10:50am - 11:10am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

11:15am PDT

Demo: Enabling Automotive Safety with Andes RISC-V IP - Marc Evans, Andes Technology

Tuesday October 22, 2024 11:15am - 11:25am PDT

Expo Hall - Exhibit Hall A - Demo Theater

Vehicles are rapidly evolving to become electrified, connected, more software-defined, and increasingly autonomous. This transformation presents a significant opportunity for open-standard RISC-V processors in automotive electronic systems, offering tailored optimization for various applications, from sensor processing and ECUs to domain, zonal, and central compute units. As the complexity of these systems continues to grow exponentially, it is crucial that the solutions adhere to rigorous standards like ISO 26262. This talk will explore these essential standards and showcase how Andes' cutting-edge solutions are designed to meet the highest levels of safety in the automotive industry.

Speakers

Marc Evans

Director of Business Development & Marketing, Andes Technology

Marc Evans recently joined Andes Technology USA as the Director of Business Development & Marketing. He has over twenty years of experience in the use of CPU, DSP, and Specialized IP in SoCs from his prior positions at Lattice Semiconductor (SoC Product Planning), Ceva (Sales and... Read More →

Tuesday October 22, 2024 11:15am - 11:25am PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

11:30am PDT

Say Goodbye to Fear, Uncertainty, and Doubt: Innovate with Codasip Studio Fusion - Keith Graham, Codasip

Tuesday October 22, 2024 11:30am - 11:48am PDT

Grand Ballroom G (Level 1)

Today’s Artificial Intelligence (AI) companies and products are at the forefront of innovation, unlocking new markets and tackling the toughest technological challenges of the future. Innovation isn’t just a buzzword; it’s the gateway to new revenue streams and higher profits. At the heart of this innovation lies the need for new architectures that push the limits of performance while slashing costs and power consumption. This is where Custom Compute comes in – transforming these groundbreaking ideas into reality. But even the most advanced tech isn’t enough if it's not the right fit. To launch game-changing products that drive growth and maximize profits, they must be developed quickly and with confidence. That’s where Codasip Studio Fusion comes in – making Custom Compute the ultimate choice by eliminating Fear, Uncertainty, and Doubt, so you can innovate boldly and lead the market.

Speakers

Keith Graham

VP of University Program, Codasip

Over my thirty-nine-year career, I've gone from designing workstations, developing multi-processor cache and memory management units, selling semiconductors, small business owner, senior instructor teaching embedded systems and computer architecture, to leading Codasip's University... Read More →

Tuesday October 22, 2024 11:30am - 11:48am PDT
Grand Ballroom G (Level 1)

AI / ML

11:30am PDT

RISC-V Needs More Secure “Wheels”! A Perspective for/from Automotive Industry - Thomas Roecker, Infineon Technologies & Sandro Pinto, OSYX Technologies

Tuesday October 22, 2024 11:30am - 11:48am PDT

Grand Ballroom H (Level 1)

The automotive industry is experiencing a massive paradigm shift. Cars are becoming increasingly autonomous, connected, and computerized. Modern E/E-architectures are pushing for an unforeseen functionality integration density, resulting in physically separate ECUs becoming virtualized and mapped to logical partitions within a single physical MCU. While functional safety has been pivotal for vehicle certification for decades, this increasing connectivity have shed light on the need for (cyber-)security and paved the way for the release of the new standard ISO21434. RISC-V has a pivotal opportunity to transform automotive computing systems, but we argue that current ISA / extensions are not ready yet. This talk provides our critical perspective on the existing limitations, particularly the upcoming WorldGuard technology, to address virtualized MCU requirements per foreseen automotive applications. We then present our proposal to address such limitations, mainly targeting master-side protection. We complete the talk by explaining the roadmap towards a full open-source Proof-of-Concept, which includes extending QEMU, an open-source RISC-V Core, and building a complete software stack.

Speakers

Thomas Roecker

Architect Automotive, Infineon Technologies

Thomas Roecker is HW/SW-architect in Automotive division of Infineon Technologies. He holds a Dr. rer. nat. in Theoretical Physics and has a background in numerical methods and computation. Thomas is focusing on HW/SW Co-Engineering in the field of dependable systems and driving introduction... Read More →

Sandro Pinto

Co-Founder, OSYX Technologies

Sandro Pinto is co-founder of OSYX Technologies. He is also Associate Research Professor at the UMinho, Portugal. Sandro has a deep academic background and several years of industry collaboration focusing on operating systems, virtualization, and security for embedded and IoT systems... Read More →

Tuesday October 22, 2024 11:30am - 11:48am PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

11:30am PDT

Sail RISC-V: Status and Future Challenges - Alasdair Armstrong, University of Cambridge

Tuesday October 22, 2024 11:30am - 11:48am PDT

Theater (Level 2)

In this talk I will present ongoing work as part of the RISC-V golden model working group to develop and maintain the Sail language and golden reference model for the RISC-V ISA. Sail is an open-source domain-specific language for ISA design and definition, which supports many use-cases, including documentation, use as a reference simulator, relaxed-concurrency semantics, hardware verification, and more.

This talk will describe our vision for the future of the RISC-V golden model. There are many challenges faced by model developers, such as the vast ecosystem of extensions and configurable options supported by RISC-V. We also need to provide a model that is more broadly useful as a source of documentation and learning for the wider RISC-V community.
I will discuss solutions for these challenges, which we intend to address both within the golden model itself, and by co-evolving Sail language itself to better support the unique needs of RISC-V. For example, we are introducing a module system for organising RISC-V extensions, a unified configuration system that supports all the aforementioned Sail use-cases, and enhanced Asciidoctor support for documentation integration.

By presenting this talk, I also hope to be able to engage further with attendees regarding their needs from a golden model.

Speakers

Alasdair Armstrong

University of Cambridge

I'm currently a research associate at Cambridge University working with Prof. Peter Sewell. In addition to developing and maintaining the Sail language, most recently I have been working on symbolic execution and relaxed-memory concurrency for Sail models, as well as formal verification... Read More →

Tuesday October 22, 2024 11:30am - 11:48am PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Any

11:50am PDT

Exploring Real-Time Operating System Execution Strategies on Virtual Machines in RISC-V Architecture - Ryosuke Yamamoto, Mitsubishi Electric Corporation

Tuesday October 22, 2024 11:50am - 12:08pm PDT

Grand Ballroom H (Level 1)

In embedded system development, several technical issues need to be solved to facilitate the transition from another architecture to RISC-V. For example, in existing embedded devices, there are products with multiple OSs, including RTOS. In such products, hardware virtualization is used to run General Purpose OS(GPOS) and RTOS to guarantee real-time performance and use GPOS software assets. However, some OSs (especially RTOS) are not intended to run on virtual machines. Therefore, we are researching a mechanism that enables all RTOSs to run even on a RISC-V virtual machine. In this talk, we will provide strategies for running the RTOS on virtual machines and the issues to be solved for its practical use.

Speakers

Ryosuke Yamamoto

Researcher, Mitsubishi Electric Corporation

Ryosuke Yamamoto is a researcher working at Mitsubishi Electric's Information Technology R&D Center. He has been researching system software such as OS and hypervisor for about 6 years. Recently, he has been interested in RISC-V architecture and developing a hypervisor for RISC-V... Read More →

Tuesday October 22, 2024 11:50am - 12:08pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

11:50am PDT

Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP

Tuesday October 22, 2024 11:50am - 12:08pm PDT

Theater (Level 2)

The Zilsd & Zclsd extensions provide load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings. The extensions are expected to be implemented in all kinds of embedded processors, with optimal performance being reached in core with a data bus of at least 64 bit - a property commonly given in superscalar implementations. The impact on code size of this extension is discussed in detail, leading to recommendations for future compiler improvements.

Speakers

Christian Herber

Senior Principal RISC-V Architect, NXP

Christian Herber is a Senior Principal RISC-V Architect at NXP, working on innovation management and technical roadmaps for RISC-V processors. He led several specification efforts, e.g. the "Load/Store Pair for RV32" RISC-V fast-track extension and the "OpenHW Group Core-V Extension... Read More →

Tuesday October 22, 2024 11:50am - 12:08pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Any

11:50am PDT

The Benefits of Building New AI Accelerators with RISC-V - Cliff Young & Martin Maas, Google DeepMind

Tuesday October 22, 2024 11:50am - 12:28pm PDT

Grand Ballroom G (Level 1)

There has been huge interest in building accelerators for AI in the decade since AlexNet ushered in the current deep learning revolution. Billions of dollars in capital have been committed, and many ambitious projects have been launched, across established manufacturers, hyperscalers, and startups. In this talk, we will reflect on our experiences at Google designing and deploying successful accelerators and the different ways that subtle challenges make effective acceleration hard. RISC-V potentially helps with these challenges, while lowering barriers to entry, reducing risks, and sharing the benefit of expertise and experience. We will make connections between our experiences and how RISC-V accelerates accelerator development itself, highlighting how the shared work on a RISC-V ecosystem for deep learning acceleration can be positive-sum, benefiting all who participate.

Speakers

Martin Maas

Staff Research Scientist, Google DeepMind

Martin Maas is a Staff Research Scientist at Google DeepMind. His research interests are in language runtimes, computer architecture, systems, and machine learning, with a focus on applying ML to systems problems. He also chairs the RISC-V J Extension Task Group, which investigates... Read More →

Cliff Young

Software Engineer, Google DeepMind

Cliff Young is a software engineer in Google DeepMind, where he works on codesign for deep learning accelerators. He is one of the designers of Google’s Tensor Processing Unit (TPU) and one of the founders of the MLPerf benchmark. Previously, Cliff built special-purpose supercomputers... Read More →

Tuesday October 22, 2024 11:50am - 12:28pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Beginner

12:10pm PDT

Automotive Solution Empowered by RISC-V Based Security and Functional Safety Module - Jianying Peng, Nuclei System Technology

Tuesday October 22, 2024 12:10pm - 12:28pm PDT

Grand Ballroom H (Level 1)

In last year’s North America Summit, Dr. Jianying Peng presented Nuclei’s NA900 (automotive) RISC-V core as the world’s 1st ASIL-D product certified RISC-V core in the automotive session. For the past 1 year, Nuclei has continued to develop functional safety solution including world’s 2nd ASIL-D product certified RISC-V core NA300 and bus fabric with safety features. Nuclei has extended the scope to information security as well. Beyond RISC-V core and bus fabric, Nuclei has released HSM (hardware security module) based on RISC-V core recently. By doing this, the position of RISC-V in the automotive ecosystem has been further strengthened with a comprehensive set of combined RISC-V based security & functional safety solutions. Thus this year we would like to share 4 topics from technical, ecosystem and business perspectives: 1. Nuclei’s experience in functional safety and security design 2. Nuclei’s experience in automotive SoC design 3. Automotive electronics software ecosystem 4. Customer success stories and open concern of RISC-V from different customers we see in the past 2 years.

Speakers

Jianying Peng

Co-founder and CEO, Nuclei System Technology

Dr Jianying Peng, graduated from School of Micro-Nano Electronics, Zhejiang University, has more than 15 years of CPU processor design and management experience. Previously Dr Peng worked in Marvell and Synopsys where she led multiple high performance processor designs in ARM and... Read More →

Tuesday October 22, 2024 12:10pm - 12:28pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

12:10pm PDT

Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Technology Co., Ltd.

Tuesday October 22, 2024 12:10pm - 12:28pm PDT

Theater (Level 2)

We introduce the practical applications and innovative explorations of RISC-V processors in the field of graphics processing.Especially the application of RVV in graphics acceleration.

Speakers

Siqi Zhao

Technology Expert, Alibaba DAMO Academy

Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community. He is currently serving... Read More →

Tuesday October 22, 2024 12:10pm - 12:28pm PDT
Theater (Level 2)

ISA and Design Tools

12:30pm PDT

Lunch (Provided for Attendees)

Tuesday October 22, 2024 12:30pm - 1:55pm PDT

Exhibit Hall B (Level 1)

Tuesday October 22, 2024 12:30pm - 1:55pm PDT
Exhibit Hall B (Level 1)

Special Events / Exhibits / Breaks

12:45pm PDT

Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks - Carl Shaw, Codasip

Tuesday October 22, 2024 12:45pm - 12:55pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

CHERI is a fine-grained memory protection technology that protects your system against buffer overflows and other memory safety issues. CHERI is implemented in hardware and enabled by supporting software. This demo simulates a real buffer overflow attack on an application running a full OS. We will show how a Codasip application core with CHERI enabled can identify the attack and stop the system without any secrets being accessed.

Speakers

Carl Shaw

Safety and Security Manager, Codasip

Prior to joining Codasip, Carl has provided security engineering and architecture consultancy to leading global electronics and semiconductor companies for more than 15 years. With a Physics Ph.D., and a career mixing electronics design in government defense, and OS and firmware development... Read More →

Tuesday October 22, 2024 12:45pm - 12:55pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

12:55pm PDT

Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine - Rejeesh Shaji Babu, Ashling

Tuesday October 22, 2024 12:55pm - 1:05pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this presentation, we will provide an overview of Ashling’s TraceLLM which offers unprecedented insights into your program’s real-time behavior through an intelligent trace capture and AI LLM based analysis software engine which can be queried using a natural language, prompt-based interface. TraceLLM, which works with the Ashling Vitra-XS hardware trace probe and RiscFree software debugger has the capability to understand the entire program execution flow and can answer any questions related to the program execution in a natural language and provide quick and accurate responses, substantially bringing down the time spent by developers for debugging. Dive into your program's behavior and watch as the intelligent engine examines the captured trace and delivers unprecedented insights including pinpointing potential bottlenecks, performance issues and offering actionable insights. Enhance efficiency, accelerate problem solving, and harness the full potential of your RISC-V systems with Ashling’s TraceLLM today.

Speakers

Rejeesh Shaji Babu

VP of Engineering, Ashling

Rejeesh Shaji babu is Ashling’s VP of Engineering with a BTech in Electronics and over sixteen years’ experience in Real-time Embedded Systems with a particular emphasis on Embedded Development Tools and Debugging.

Tuesday October 22, 2024 12:55pm - 1:05pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

1:05pm PDT

Demo: More Than Point Tools: RISC-V Solutions - Larry Lapides, Synopsys

Tuesday October 22, 2024 1:05pm - 1:15pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

As RISC-V adoption grows, how are EDA tools and IP adapting to address new and evolving design challenges? From architecture exploration to design implementation and software development, SoC designers are looking for ways to take advantage of the RISC-V ecosystem and deliver optimized products with fast time-to-market. At Synopsys, we’re building RISC-V solutions to help customers from the beginning of the project to delivery and deployment, supporting the full RISC-V ISA plus custom instructions while enabling architecting of workload-optimized processors, comprehensive processor verification, and pre-silicon software development. Whether you are building your own RISC-V core, using a partner’s core, or implementing Synopsys ARC-V processor IP, Synopsys can help you meet your project requirements. This presentation will provide an overview of the broad range of Synopsys RISC-V solutions that have been proven by our customers taking RISC-V SoCs to silicon.

Speakers

Larry Lapides

Sr. Dir. Product Management, Synopsys

Larry Lapides is the Executive Director of Business Development at Synopsys, responsible for ImperasDV RISC-V processor verification products. He came to Synopsys through the acquisition of Imperas, where he was a founding member and VP Worldwide Sales and Marketing. Larry has also... Read More →

Tuesday October 22, 2024 1:05pm - 1:15pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

1:55pm PDT

Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here - Jin Kim, Esperanto Technologies

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Grand Ballroom G (Level 1)

The size of the Foundation models behind the Generative AI revolution have grown at a rate of more than 400x every 2 years, while DRAM memory capacity has been increasing only at 2x every two years, leading to what is commonly called the “memory wall”. Similarly, while the required throughput rate of LLMs making up the Foundation models has been increasing at 10x per year, the increase in computational capability of GPUs has been at a pace of only 10x in 4 years, leading to what is commonly called the “compute wall”. These trends have raised a new set of challenges in how to economically train these models, cost-effectively run them, and manage the tremendous increase in electrical power. The first contribution of this session are lessons learned in leveraging hardware and software developed for traditional AI workloads and how it was extended to support Generative AI. The session’s next main contribution is how we are applying lessons learned from our first-generation technology to our next generation. In this session’s final contribution, we will also discuss how the RISC-V ISA could be extended in ways that would make it more efficient and compelling at running Generative AI.

Speakers

Jin Kim

Chief Data Science Officer, Esperanto Technologies

An executive, entrepreneur, and data scientist, Jin’s experience spans enterprise software products and services in AI, big data, and advanced analytics. He has led multinational engineering teams at both established and startup companies, including GraphSQL, Wave Computing, Objectivity... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

1:55pm PDT

CPU Security in the Context of RISC-V - Sylvain Guilley, Secure-IC

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Grand Ballroom H (Level 1)

Ensuring security in Central Processing Units (CPUs) has become a critical concern. This presentation examines the importance of CPU security in the context of RISC-V , with a focus on addressing potential vulnerabilities through various security measures. In the presentation we explore and analyze different types of cyber-attacks relevant to RISC-V CPUs, such as code injection, buffer overflows and jump-orienting programming but also cyber-physical attacks like side-channel attacks, fault injections, and supply chain attacks such as hardware Trojans. We discuss the concept of Lockstep as a redundancy technique and Code & Control-Flow Integrity verification (CCFI) to enhance security and safety by detecting and correcting errors or malicious manipulations. Additionally, the presentation emphasizes the significance of industry-standard certifications (Common Criteria, FIPS 140-3) in verifying the effectiveness of security solutions. Finally, we explain why, by understanding and implementing robust security measures, RISC-V CPUs can establish a strong foundation for secure computing environments, safeguarding against diverse cyber threats and risks.

Speakers

Sylvain Guilley

Co-Founder and CTO, Secure-IC

Sylvain Guilley is co-founder and CTO at Secure-IC. Sylvain is also professor at Télécom Paris (Institut Polytechnique de Paris), associate research at the École Normale Supérieure (ENS), and adjunct professor at the Chinese Academy of Sciences (CAS). His research interests include... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Advanced

1:55pm PDT

Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc.

Tuesday October 22, 2024 1:55pm - 2:13pm PDT

Theater (Level 2)

Traditional post silicon HW debug data collection involves the gathering of a snapshot of the design state at the point of failure using scan and an array dump. We propose a hardware mechanism called Debug Signal Trace (DST) that provides the ability to trace a set of design signals over multiple cycles leading to the point of the failure and to store the trace to an on-chip memory like SRAM, or to off-chip System memory. Post processing of the stored debug trace data not only gives debug visibility, but also the ability to build post silicon coverage points. Debug Signal Trace data is timestamped to correlate with instruction trace data. This extends the use-case to SW performance analysis. To ease adoption and usability, the DST control register definition mirrors that of the RISC-V Trace Control Interface which is familiar to the RISC-V debug community. DST supports signal compression to minimize the memory storage footprint. DST leverages the triggers specified in RISC-V Debug Spec while adding user configurable triggers using a select set of design signals.

Speakers

Sajosh Janarthanam

Principal Engineer, Tenstorrent Inc.

Sajosh has over 20 years of experience in the semiconductor industry, participating in various stages of chip design, from microarchitecture development to post-silicon debug. Currently at Tenstorrent, he is working on RISC-V CPUs and AI SoCs that scale to meet different PPA (Power/Performance/Area... Read More →

Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Beginner

2:15pm PDT

Building Tool Chains for RISC-V AI Accelerators - Jeremy Bennett, Embecosm

Tuesday October 22, 2024 2:15pm - 2:33pm PDT

Grand Ballroom G (Level 1)

Our client is developing a massively parallel 64-bit chip for AI inference workloads. To facilitate early software development, we are bringing up an AI tool flow for this chip in a QEMU RISC-V environment. In this talk, we'll share our experience of getting three key AI frameworks working with RISC-V QEMU: Pytorch, Tensorflow and the OpenXLA compiler. Our talk will share our experience addressing two key issues. We will describe the challenges we faced, their solutions and reflect on the lessons learned for future work. The first of these is simply getting the tools to effectively run in an emulated RISC-V environment. These tools are large, fast moving pieces of software with extensive external dependencies. Our second challenge is performance. AI workloads are inherently parallel, and hence run efficiently on vector enabled hardware. However RISC-V vector (RVV) is relatively new, and we experienced difficulty getting the performance we expected out of the tool flow. At the end of this talk, we hope our audience will have a better understanding of the challenges in bringing up an AI tool flow under QEMU. We hope out experience will help them bring up their own AI tool flows.

Speakers

Jeremy Bennett

Chief Executive, Embecosm

Bio: Dr Jeremy Bennett is founder and Chief Executive of Embecosm(http://www.embecosm.com), a consultancy implementing open sourcecompilers, chip simulators and AI/ML for major corporations around the world.He is a author of the standard textbook "Introduction to CompilingTechniques... Read More →

Tuesday October 22, 2024 2:15pm - 2:33pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

2:15pm PDT

An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications - Jamie Kim, Samsung Electronics

Tuesday October 22, 2024 2:15pm - 2:33pm PDT

Grand Ballroom H (Level 1)

I would like to introduce our success story of adopting RISC-V CPU in the embedded domain with the ability to customize the architecture. For this success, we developed a scalable, orthogonal and transparent interrupt architecture which enabled the control of extremely timing-critical tasks. I believe this architecture can be widely adopted across multiple domains with the configurability to adopt to their own requirements.

Speakers

Jamie Kim

Principal Engineer, Samsung Electronics

Jamie Kim received Ph.D. degree on Computer Architecture back in 2015 and has been working in System LSI, Samsung ever since. He led multiple MCU projects using RISC-V, which successfully went to mass production, including the first ever RISC-V based product in Samsung. Currently... Read More →

Tuesday October 22, 2024 2:15pm - 2:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

2:15pm PDT

RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS

Tuesday October 22, 2024 2:15pm - 2:53pm PDT

Theater (Level 2)

The RISC-V Foundation's Olympia Performance Model is a great tool as the basis for designing a high-performance RISC-V CPU design. This session will provide a high-level overview of the Olympia Performance Model and then provide examples of how to use the model for tradeoff analysis on different RISC-V Out-of-Order superscalar designs.

Speakers

Knute Lingaard

Sr. Principal Engineer, MIPS

Sr. Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. Lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians and co-chair of the RISC-V International Performance Modeling SIG

Tuesday October 22, 2024 2:15pm - 2:53pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

2:35pm PDT

LLM Inference on RISC-V Embedded CPUs - Yueh-Feng Lee, Andes Technology

Tuesday October 22, 2024 2:35pm - 2:53pm PDT

Grand Ballroom G (Level 1)

The advancement of large language models (LLMs) has significantly enhanced natural language processing capabilities, enabling complex text understanding and generation tasks. This presentation focuses on optimizing the open-source LLaMA CPP project for the RISC-V P extension. By running the TinyLLaMA 1.1B model on the Andes Voyager development board using a quad-core CPU supporting the RISC-V P extension, performance results show that the model can achieve near real-time response. This work highlights the potential of RISC-V as an efficient platform for deploying advanced AI models in resource-constrained environments, contributing to the growing field of edge computing and embedded AI applications.

Speakers

Yueh-Feng Lee

Manager, Andes Technology

Yueh-Feng Lee received his Ph.D. degree in computer science from National Chiao Tung University. He previously worked at Mediatek and Industrial Technology Research Institute. His areas of focus include AI compiler and runtime, hypervisor technology, and embedded systems.

Tuesday October 22, 2024 2:35pm - 2:53pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Intermediate

2:35pm PDT

Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android - Lev Rumyantsev & Jeremiah Griffin, Google

Tuesday October 22, 2024 2:35pm - 2:53pm PDT

Grand Ballroom H (Level 1)

Berberis is an open source userspace dynamic binary translator facilitating cross-architecture development and testing of RISC-V Android applications. It translates native riscv64 code inside of an Android APK to x86_64 at runtime, enabling developers to test RISC-V builds of their apps on their workstations when target device hardware is unavailable. This presentation will cover the motivation and benefits of userspace translation versus whole-system emulation, the challenges of translating RISC-V code to x86_64, and use cases and future directions for the project.

Speakers

Jeremiah Griffin

Staff Software Engineer, Google

Jeremiah joined Google in 2022 and has been a technical lead of the Berberis RISC-V-to-x86 dynamic binary translator for Android since 2023. His areas of expertise include systems programming, automated testing, embedded and automotive software, and human-machine interfaces. He has... Read More →

Lev Rumyantsev

Software Engineer, Google

Since 2014 Lev has been working at Google on various projects to enhance user experience with Android applications on Large Screen and x86 devices. His main focus has been on developing a binary-translation layer to run ARM-compiled applications on x86 devices. In 2022 Lev also started... Read More →

Tuesday October 22, 2024 2:35pm - 2:53pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

2:55pm PDT

The Future of Mission Critical Edge Compute Is RISC-V - David Levy, Microchip

Tuesday October 22, 2024 2:55pm - 3:13pm PDT

Grand Ballroom H (Level 1)

Mission Critical Edge Compute demands high-performance MPUs with time and space partitioning capabilities to enable mixed-criticality workloads. As well, the MPUs must be built with comprehensive fault-tolerance and fault-isolation capabilities. Given these requirements, A&D and Industrial systems developers worldwide are looking to RISC-V as a key enabling technology to enable their next-generation platforms. This presentation will explore: 1) Why RISC-V for Mission Critical Edge Compute: Virtualization, Vector Processing, and WorldGuard Partitioning 2) How RISC-V is set to transform space computing 3) The opportunities for RISC-V in aviation 4) Applications for RISC-V in industrial applications This presentation will conclude with how Microchip is responding and a call-to-action for what is needed from the RISC-V ecosystem to fully capitalize on this once in a generation opportunity to transform critical infrastructure.

Speakers

David Levy

Senior Technical Staff Engineer, Product Marketing, Microchip

David recently joined Microchip in October of 2023. David brings over 30 years of Semiconductor experience that spans both business and technical acumen. David's team develops 64-bit computing solutions and high-bandwidth network communication solutions.

Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Any

2:55pm PDT

Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys

Tuesday October 22, 2024 2:55pm - 3:13pm PDT

Theater (Level 2)

With the increased usage of RISC-V processors across the whole range of SoC market segments, quality of the RISC-V processor is an increasingly important issue. Historically, processor IP has been purchased from single-source vendors who own the ISA, and this IP was assumed to be of excellent quality. However, in the RISC-V ecosystem with vendor-supplied IP, open source IP and IP developed in-house, such quality cannot be taken for granted. This creates a verification “disconnect” between SoC developers expecting high-quality IP and processor developers that do not have the verification resources of the single source processor IP vendors. This talk will discuss how dynamic and formal methods can be used together for a more thorough and efficient verification process, helping to bridge the verification disconnect. Examples of using this combined methodology on open-source cores from OpenHW Group, specifically the CV32E40 family, CVW and CVA6, will be presented, including functional coverage results. A key feature of the RISC-V ISA is its extensibility, enabling custom instructions and CSRs to be added. The combined approach will also be shown to work well in this common situation.

Speakers

Aimee Sutton

Sr. Dir. Product Management, Synopsys

Aimee is currently Sr. Dir. Product Management at Synopsys, responsible for solution for RISC-V processor verification and system test generation. She has been involved in the design verification space for over 20 years, as both an EDA tool user and EDA tool developer, with Metrics... Read More →

Xiaolin Chen

Sr. Director, Applications Engineering, Synopsys

Xiaolin Chen is a Sr. Director of Applications Engineering, formal solutions at Synopsys. She leads a team of applications engineers providing guidance, training, assistance and consulting to semiconductor customers to successfully develop formal technology in verification flow. The... Read More →

Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Beginner

2:55pm PDT

Bridging the Gap: Compiling and Optimizing Triton Kernels Onto RISC-V Targets Based on MLIR - Aries Wu, Terapines Technology Co., Ltd.

Tuesday October 22, 2024 2:55pm - 3:33pm PDT

Grand Ballroom G (Level 1)

This deep dive will explain an end to end software stack solution to RISC-V based AI chips, including an innovation way to write AI kernels with new programming languages such as Triton (and Mojo later), using MLIR/LLVM based AI compiler infra to lower Triton kernels and neural networks from frameworks such as Pytorch, ONNX, Tensorflow and JAX into a range of high/middle/low level of MLIR dialects to do coarse grained high level optimizations such as loop tiling, kernel fusion, auto-vectorization etc. This paves the way of sharing common open source Triton kernels libraries provided in PyTorch and other frameworks, and greatly reduces the adoption time for AI software stack to RISC-V based AI chip. This talk will also explore the limitation of Triton language, and how can we extend the Triton language, and also the MLIR conversion and optimization passes to better support non GPU architecture target such as RISC-V.

Speakers

Aries Wu

CTO, Terapines Technology Ltd

Co-founder & CTO of Terapines Technology. More than 15 years compiler design and development experience in Andes, S3 Graphics, Imagination and Terapines. Specialized in CPU, GPU, GPGPU, AI compilers based on MLIR, LLVM and GCC.

Tuesday October 22, 2024 2:55pm - 3:33pm PDT
Grand Ballroom G (Level 1)

AI / ML

Audience Experience Level Advanced

3:15pm PDT

Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension - Markku-Juhani O. Saarinen, Tampere University

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Grand Ballroom H (Level 1)

Version 1.0.0 of the RISC-V Vector Cryptography extensions specification was ratified in late 2023 and adds high-performance cryptography operations to the comprehensive list of ISA features that RISC-V officially supports. We present the first open-source implementation of the RISC-V Vector Cryptography specification, using the PULP Project's Ara vector processor as a baseline and targeting a 28nm technology node. We present the design/verification opportunities and challenges that were encountered. Furthermore, a detailed review of the implementation and benchmarking results will be included in the presentation.

Speakers

Markku-Juhani O. Saarinen

Professor of Practice, Tampere University

Markku-Juhani O. Saarinen is a Professor of Practice (työelämäprofessori) at Tampere University (Finland). A cryptographer by training and with a long international career in security engineering, Markku has co-authored many of the ratified RISC-V cryptography extensions. Currently... Read More →

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Grand Ballroom H (Level 1)

Automotive / Embedded / Industrial

Audience Experience Level Intermediate

3:15pm PDT

Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm

Tuesday October 22, 2024 3:15pm - 3:33pm PDT

Theater (Level 2)

QEMU is an emulator that developers can developer and debug their software on it before getting the real RISC-V hardware. We observed that vectorized executables run much slower than non-vectorized ones on QEMU. From benchmarks (e.g. SPEC CPU2k6 h264), we can see that most of the execution time is occupied by RVV load/store instructions. The same observation has been reported in the QEMU community. For example, the glibc memcpy benchmark runs 2x to 60x slower than its scalar equivalent on QEMU. We aim to improve the performance of RVV instructions in QEMU, thereby reducing the execution time required for tasks such as Android bootup. In this talk, we will provide an overview of how we enhanced the performance of QEMU RVV load/store instructions and discuss future work.

Speakers

Jeremy Bennett

Chief Executive, Embecosm

Max Chou

Engineer, SiFive

Max Chou is a Staff Software - Systems Development Engineer at SiFive. His research interests include binary translation, debugging, optimizations, performance and program analysis tools.

Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Theater (Level 2)

ISA and Design Tools

Audience Experience Level Intermediate

3:35pm PDT

HPC & Data Center Poster Sessions

Tuesday October 22, 2024 3:35pm - 4:15pm PDT

Expo Hall - Exhibit Hall A (Level 1)

Implementing and Verifying RISC-V Nexus Trace Compliant Trace Encoder for High Performance Cores - Sajosh Janarthanam, Tenstorrent Inc.
In this poster, we present the N-trace infrastructure, which supports instruction tracing for multiple out-of-order RISC-V cores. We discuss the architectural and microarchitectural decisions involved in designing the Encoder. Furthermore, we describe the infrastructure established to facilitate efficient trace transmission. Finally, we discuss the strategies employed to verify the Encoder and its associated components.

Speakers

Sajosh Janarthanam

Principal Engineer, Tenstorrent Inc.

Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Expo Hall - Exhibit Hall A (Level 1)

Poster Sessions, HPC + Data Center

3:35pm PDT

ISA & Design Tools Poster Sessions

Tuesday October 22, 2024 3:35pm - 4:15pm PDT

Expo Hall - Exhibit Hall A (Level 1)

RISC-V "V" Vector Extension (RVV) with Reduced Number of Vector Registers - Eino Jacobs & Dmitry Utyanski, Synopsys
Reduce the number of vector registers to reduce the area of small processors for DSP applications.

MAMBO: Dynamic Binary Modification on RISC-V - John Kressel & Mikel Lujan, University of Manchester
Dynamic Binary Modification (DBM) is an important technique used in computer architecture simulators, virtualization, and program analysis, to name a few examples. The software ecosystem of RISC-V is maturing at pace, but is still missing a high-performance, optimized DBM. Addressing this requirement is key to improving the overall software ecosystem. This paper presents a comprehensive performance evaluation study for a DBM (MAMBO) which has been ported and optimized for 64-bit RISC-V. The main optimizations for DBM on RISC architectures have been implemented and tuned for RISC-V to address specific architectural features. For example, jump trampolines have been specifically developed to address the short direct branch range specified by the RISC-V ISA. The evaluation shows that for SPEC CPU2006 the geometric mean overhead is of 14.5%, with SPECint having the largest contribution with a geometric mean of 28.5%, while SPECfp has only an overhead of 5.6%. Concretely, this results in a reduction in runtime for h264ref from over 75 hours using the baseline DBM, to 2.2 hours with optimizations applied.

TestRIG - Professor Simon Moore, University of Cambridge
TestRIG is a framework for directed randomized testing of RISC-V cores. It leverages the QuickCheck automatic testing library and the RISC-V sail model to find potential trace divergences and report minimal instruction sequences triggering a bug in an implementation, helping with RTL bring-up and debugging.

MXM-RVV: Easy Multicore X Multithreading with Vectors via Composable Extensions + DMA - Joseph Maheshe, Guy Lemieux & Brandon Freiberger, University of British Columbia
We revisit the topic of multithreaded vector processors, but now within the RISC-V architecture. By combining data-level and thread-level parallelism, we further improve performance. We create an SoC with one hart and multiple RVV vector units, where each vector unit contains multiple contexts (multithreading), using the Draft CX Specification. We add an independent instruction queue to each context within each vector unit, thereby enabling asynchronous multicore, multithreaded execution of vector instructions with a single scalar thread and hardware scheduling of the parallel queues.
To make this work, we show that non-blocking vector loads and stores are essential to hide memory latency by executing instructions from other contexts. We use a round-robin scheduling scheme for fine-grained multithreading. We illustrate how to write software to target the MXM-RVV and show that it requires minimal changes.

Open-Source Self-Checking RISC-V Architectural Tests - Darshak Koshiya, Tenstorrent Inc.
This presentation introduces a collection of self-checking RISC-V Instruction Set Architecture (ISA) directed tests designed to help streamline the verification process for RISC-V designs. These tests leverage an end-of-test mechanism, that eliminates the need for pre-defined expected outputs and simplifies test execution. These open-source tests employ randomly generated operands and data avoiding the pitfalls of the using simple constants.This presentation will delve into the design and implementation details of these pen-source tests, showcasing their effectiveness in the verification of RISC-V ISA implementations and facilitating a more streamlined verification process for RISC-V cores.

Emulation-Friendly, Efficient, Self-Checking RISC-V Compliant JTAG-DFD Testbench Mechanism - Pravin Tavagad & Midhun Varman, Tenstorrent
The increasing complexity of modern electronic systems and RISC-V based SoC designs demands robust testing methodologies to ensure reliability and performance. JTAG testbenches have become essential tools for debugging and verifying integrated circuits. However, traditional JTAG testbenches often face challenges in terms of emulation friendliness, efficiency, quick turn around time, reusability and scalability. We present an approach that addresses the critical need for an advanced JTAG testbench for complex RISC-V based designs that overcomes these limitations. Additionally, our approach supports access to various RISC-V components such as the RISC-V Debug module via the RISC-V Debug Transport Module (DTM), the RISC-V compliant Trace module

Simplifying Sail and Architecture Compatibility Testing Setups with Containers - Greg Sterling, RISC-V International

RISC-V Documentation Guidelines: Is it 'Which' or 'That'? - Kersten Richter & Bill Traynor, RISC-V International

Speakers

Bill Traynor

RISC-V International

Greg Sterling

Technical Community Architect, RISC-V International

Kersten Richter

Senior documentation Architect, RISC-V International

I enjoy reading, baking, canning, pets, hiking, national parks, and most of all, documentation!

Brandon Freiberger

M.A.Sc Student, University of British Columbia

Eino Jacobs

Sr. Architect, R&D, Synopsys

Eino Jacobs has decades of experience with architecture and design of high-performance processors. He works now on RISC-V Vector processors. He is also a lead architect and designer of the VPX and ARC processor product lines at Synopsys.

Darshak Koshiya

Principal Engineer, Tenstorrent Inc.

Darshak Koshiya is a Principal Engineer at Tenstorrent, involved in design of hardware to accelerate AI workloads and high performance CPU. He is currently involved with the core verification of RISC-V high performance CPU design.Prior to joining Tenstorrent, Darshak was a Senior... Read More →

John Kressel

PhD Student, The University of Manchester

John Alistair Kressel is a PhD student and research assistant in the Advanced Processor Technology (APT) group at the University of Manchester. He recently completed his MPhil researching software compartmentalization using CHERI hardware capabilities. His interests include software... Read More →

Guy Lemieux

Professor, University of British Columbia

Guy is a Professor in Computer Engineering at the University of British Columbia where he teaches digital design and computer systems/architecture courses. His research focuses on improving FPGA devices and CAD tools, in particular making them easier to use and more efficient for... Read More →

Mikel Lujan

Professor, University of Manchester

Mikel Luján received the PhD degree in computer science from The University of Manchester, U.K., in 2002. He is currently a professor with the Department of Computer Science, The University of Manchester, where he holds the Royal Academy of Engineering Research Chair on Computer... Read More →

Simon Moore

Professor, University of Cambridge

Pravin Tavagad

Staff Engineer, Tenstorrent

Pravin Tavagad is currently working as CPU DV Staff engineer at Tenstorrent Bangalore.His areas of interests are CPU, Memory subsystem and SoC Design verification.Prior to joining tenstorrent he has worked on various architectures like x86_64, ARM, Tensilica xtensa.

Dmitry Utyanskiy

Sr. Architect Sw Engineering, Synopsys

Dmitry Utyanskiy has been involved in embedded software development and Digital Signal Processing algorithms design, optimization and application for communications, RADAR, audio and image processing since his graduation from St. Petersburg Electrotechnical University in 1994. Currently... Read More →

Midhun Varman

RISC V Intern, Tenstorrent

B Midhun Varman has been part of Tenstorrent for the past one year .In his current role, he is responsible for Verification of High-Performance RISC-V cores specifically in the JTAG module and building various cluster level tests. He holds a B.Tech and M.tech in Electrical Engineering... Read More →

Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Expo Hall - Exhibit Hall A (Level 1)

Poster Sessions, ISA + Design Tools

3:35pm PDT

Security Poster Sessions

Tuesday October 22, 2024 3:35pm - 4:15pm PDT

Expo Hall - Exhibit Hall A (Level 1)

Commercializing CHERI on a Codasip A730 RISC-V Application Core - Tariq Kurd, Codasip
Memory safety continues to cause widespread and costly cyber security problems. Data breaches often arise from memory safety vulnerabilities leading to multi-million dollar losses for victims; for example, losses due to the well-known OpenSSL Heartbleed bug are estimated to exceed $500 million. Therefore, there is increasing interest in the Capability Hardware Enhanced RISC Instructions (CHERI) which is an ISA extension that mitigates memory safety vulnerabilities by design. CHERI has been primarily a research project until now! The University of Cambridge, which originated the technology, partnered with Codasip to propose a CHERI extension for RISC-V. Codasip also unveiled the first commercial implementation of a CHERI RISC-V: the A730 processor. In this poster, we introduce the A730 processor microarchitecture and highlight the main challenges to supporting CHERI RISC-V. We also describe the key differences between A730 implementations with and without CHERI support. In our experience, the A730 with CHERI is about 4% larger in area than an A730 without CHERI.

CHERI RISC-V Standardization - Peter Rugg, University of Cambridge
CHERI is a cross-architecture security technology, adding memory safety and compartmentalization features via capability support in the hardware. This poster will present the current effort to standardize the architectural extensions required to obtain these benefits in RISC-V: currently an effort shared by University of Cambridge, Codasip, Google, and others. The standardization work has been proceeding at pace, with a concrete specification document available, and extensive community interaction to iron out edge cases and ensure applicability to a wide range of uses.

The CHERI Alliance – Getting the Industry Together to Tackle a $10T / Year Problem - Mike Eftimakis, CHERI Alliance
Cybercrime costs the World more than $10T / year, and this amount is growing at an alarming rate. A study of software vulnerabilities has shown that over the past 20 years, memory attacks represented more than 70% of them. CHERI technology has been developed to solve the problem and has been proven to work. After 14 years of research and prototyping, CHERI is now ready to get out of the lab! A new CHERI SIG has been formed in RISC-V International, but adoption won’t happen without a significant industry-led effort: this is the goal of the CHERI Alliance.

Speakers

Tariq Kurd

Distinguished Engineer and Lead IP Architect, Codasip

I have been chair of RISC-V code-size, and Zfinx, and these days am heavily involved in CHERI standardisation for RISC-V.

Mike Eftimakis

Founding Director of the CHERI Alliance, CHERI Alliance

Mike Eftimakis has an extensive background in the electronics industry with 30 years in senior technical and business roles. He has been innovating with companies like VLSI Technology, NewLogic or Arm.He is now VP Strategy and Ecosystem at Codasip, where he drives the long-term vision... Read More →

Peter Rugg

Research Associate, University of Cambridge

Peter Rugg is a Research Associate in hardware security at the University of Cambridge. Since completing his PhD in 2023, he has continued his research on extending processors with architectural security features, with a focus on efficient, deterministic protection. Particular areas... Read More →

Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Expo Hall - Exhibit Hall A (Level 1)

Poster Sessions, Security

3:35pm PDT

Coffee Break

Tuesday October 22, 2024 3:35pm - 4:15pm PDT

Exhibit Hall A

Tuesday October 22, 2024 3:35pm - 4:15pm PDT
Exhibit Hall A

Special Events / Exhibits / Breaks

3:40pm PDT

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics

Tuesday October 22, 2024 3:40pm - 3:50pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this talk we will cover the latest developments in running modern transformers , such as LLama-2, on Semidynamics RISC-V "All-In-One" solution, comprising a core, a Vector Unit and a Tensor Unit. In this talk you'll learn about how ONNX RT is used to deploy modern models on Semidynamics solution, on how the ratio of the vector to tensor compute is important for balanced execution and how the all-in-one can be scaled-out to reach different performance
levels.

Speakers

Roger Espasa

CEO & Founder, Semidynamics

Roger Espasa is the founder and CEO of Semidynamics, a European IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected... Read More →

Tuesday October 22, 2024 3:40pm - 3:50pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

3:50pm PDT

Demo: Super-optimized Ubuntu and Open Source on RISC-V - Gordan Markuš, Canonical

Tuesday October 22, 2024 3:50pm - 4:00pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In this session, Canonical will introduce the work being done by the organization to optimize Ubuntu, the most popular Linux operating system, for RISC-V. We will present the Canonical roadmap and vision for Ubuntu on RISC-V, this will include:

Ubuntu and Canonical roadmap for RISC-V profiles
How to enable vendor differentiation and make the unique vendor IP shine in Ubuntu
We will present the depth of our partnerships and contributions towards open source and community projects via RISC-V International and RISE

Speakers

Gordan Markuš

Director, Silicon Alliances, Canonical

With more than a decade in engineering, business development, and leadership roles working with open source software, Gordan is a leader in Canonical's Silicon Alliances organization, developing strategic relationships with the RISC-V ecosystem and various other semiconductor companies... Read More →

Tuesday October 22, 2024 3:50pm - 4:00pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

4:00pm PDT

Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V - Kelvin Low, Samsung Foundry

Tuesday October 22, 2024 4:00pm - 4:10pm PDT

Expo Hall - Exhibit Hall A - Demo Theater

In an era defined by rapid technological advancement, the intersection of semiconductor process innovation and artificial intelligence is reshaping industries and driving new paradigms of computing. This talk explores the key market trends, growth forecast and factors driving new use cases. We will also share how Samsung Foundry is enabling customer innovations in particular around RISC-V where chip and chiplet performance optimization resulting in smarter and more efficient systems. By examining current trends and future prospects, we aim to illuminate the path forward for engineers, developers, and decision-makers in harnessing the power of silicon technologies, advanced packaging, RISC-V and AI to create cutting-edge solutions that meet the demands of a rapidly evolving digital landscape.

Speakers

Kelvin Low

Vice President, Market Intelligence, Marketing & Partnerships, Business Strategy and Business Development, Samsung Foundry

Kelvin Low serves as the Vice President of Samsung Foundry Market Intelligence, Marketing &Partnerships, Business Strategy and Business Development teams. Prior to rejoining SamsungSemiconductor, he was the CEO and General Manager for SEMIFIVE US Inc and held otherTechnology, Marketing... Read More →

Tuesday October 22, 2024 4:00pm - 4:10pm PDT
Expo Hall - Exhibit Hall A - Demo Theater

Demo Theater

4:15pm PDT

Keynotes: Making RISC-V Real, Fast! - Yuning Liang, CEO, DeepComputing & Nirav Patel, Founder and CEO, Framework

Tuesday October 22, 2024 4:15pm - 4:30pm PDT

Mission City Ballroom B2 - B5 (Level 1)

The RISC-V ISA is one of the most exciting recent developments in computing with amazing potential to revolutionise applications and industries worldwide. But what does it take to bring consumer products to market based on this young ISA? This session will explore how DeepComputing and their partners worked together to develop a range of products including the first RISC-V based laptop and tablet. It will detail the risk taking, collaboration, learning and accelerated technical development needed to put these products into the hands of consumers worldwide. Come and be inspired, maybe next year’s biggest RISC-V based product could be designed by you.

Speakers

Nirav Patel

Founder and CEO, Framework

Nirav Patel is the Founder and CEO of Framework, makers of the Framework Laptop.

Yuning Liang

CEO, DeepComputing

Yuning is the founder and CEO of Xcalibyte and Advisor of DeepComputing which makes RISC-V SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.Yuning’s career took him from UK to Switzerland to South Korea and finally to China. He comes... Read More →

Tuesday October 22, 2024 4:15pm - 4:30pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:30pm PDT

Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective - David Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley

Tuesday October 22, 2024 4:30pm - 4:45pm PDT

Mission City Ballroom B2 - B5 (Level 1)

10 years ago, David Patterson and Krste Asanović made the case for RISC-V as an open Instruction Set Architecture with the vision that it become the standard ISA for all computing devices. In this session, David Patterson revisits the arguments we made in that paper and the objections to it at the time then gives his views of the progress made in the subsequent decade and his thoughts on the future.

Speakers

David Patterson

Pardee Professor of Computer Science, Emeritus, University of California at Berkeley

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976.Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of... Read More →

Tuesday October 22, 2024 4:30pm - 4:45pm PDT
Mission City Ballroom B2 - B5 (Level 1)

Keynote Sessions

4:50pm PDT

Keynote Panel: Powering Local Innovation and Global Success with RISC-V - Alessandro Campos, Ministry of Science, Technology, Innovations; Jianying Peng, Nuclei System Technology; Roger Espasa, Semidynamics; Ted Speers, Microchip; Calista Redmond, RISC-V

Tuesday October 22, 2024 4:50pm - 5:30pm PDT

Mission City Ballroom B2 - B5 (Level 1)

The impact of computing on our modern world is profound, changing our daily life with new ways to communicate, work, and play. Until now, advances in computing have been led by a limited number of companies and countries. RISC-V has changed everything and taken down the barriers to entry. As the industry standard ISA, RISC-V has opened doors for companies big and small, universities and research institutes, and even governments to engage in the global digital economy. RISC-V enables engineers and developers worldwide to innovate locally, with access to a global ecosystem and market. In this panel, we gather experts from around the world to discuss how RISC-V is changing computing in their geography through direct investments, collborations, and incentives to build a bright digital future.

Moderators

Calista Redmond

CEO, RISC-V International, RISC-V International

Speakers

Alessandro Campos

General Coordinator of Semiconductor, Ministry of Science, Technology, Innovations

Alessandro Augusto Nunes Campos, Doctor in Science in Electrical Engineering - Semicon, Bachelor in Computer Engineering and Civil Engineering, worked in research in Aerospace, Information and Communication Technology (ICT), Semiconductors and Engineering. He has taught at renowned... Read More →

Keynote Sessions

5:30pm PDT

Attendee Reception and Booth Crawl Sponsored by Ventana

Tuesday October 22, 2024 5:30pm - 7:00pm PDT

Exhibit Hall A

Tuesday October 22, 2024 5:30pm - 7:00pm PDT
Exhibit Hall A

Special Events / Exhibits / Breaks