RISC-V Summit

For RISC-V to be successful, industry confidence in the quality of produced cores is critical, driving the mission of the RISC-V International Certification Steering Committee (CSC). It is recognized that a high degree of commercial-grade testing is required, leveraging tests from verification specialists, as well as existing work. The CSC has noted the need for small and large core certification, as well as the SoC components around them.

This presentation will analyze the CSC requirements and detail the types of tests that are likely be required, given the focus on architectural analysis that goes much further than basic ISA compliance. We will discuss the kind of scenarios to be validated, and how this can best be accomplished using the required self-checking content. The certification tests could also form the foundation of a comprehensive microarchitectural verification suite. While this is not the goal of certification, we will demonstrate how this might benefit overall verification.

Attendees will gain a greater understanding of the implementation of a certification flow as part of a broader verification approach, and the impact on this on their cores or SoCs.

The powerhouse which unlocks the ability to simulate complex, real world problems, as well as powering AI and ML workloads, High Performance Computing (HPC) is a crucial part of the modern day world. Supercomputers most commonly leverage x86 CPUs and Nvidia or AMD GPUs, however, as the ever-increasing demand by users for more capability meets a growing focus on sustainability, alternative technologies such as RISC-V are important.

RISC-V can offer benefits in performance and energy efficiency to HPC through the potential for specialisation, however the HPC community is yet to embrace RISC-V. But with increased availability of commodity RISC-V high performance CPUs (e.g. the SG2042) and PCIe accelerator cards, RISC-V is becoming a more serious option.

In the RISC-V HPC SIG our role to help drive adoption, and in this talk I will describe where the RISC-V ecosystem currently lies for HPC, explore performance and energy efficiency of latest generation RISC-V hardware against that currently more commonplace in HPC, and highlight key areas that we as the RISC-V community should prioritise to drive RISC-V adoption in HPC. Ultimately acting as a call to action for the RISC-V community.

The Performance Analysis SIG works to improve the state of performance analysis on RISC-V systems, by overseeing both the development of new ISA extensions to improve visibility, and the enabling of the software ecosystem (firmware, OS, tools). In this talk, chair Beeman Strong and member Atish Patra will recap the work completed in the last year, including 4 new ISA extensions and several improvements to Linux perf, and introduce some ongoing work. This will include progress updates on the Performance Events TG, the Performance Event Sampling TG, the Self-hosted Trace TG, and further Linux kernel/perf tool enhancements that aim to allow performance analysis on RISC-V to match or exceed the experience on competing ISAs.

This session aims to cover ISA and non-ISA for Confidential VM Environment (CoVE) on RISC-V platforms. The session will describe the use of ratified RISC-V privileged ISA extensions and new priv. ISA extensions called "Supervisor Domains" that are proposed and reaching task group consensus. This session will also describe the specifications for proposed non-ISA/ABI extensions and SoC requirements that enable Confidential Computing on RISC-V-based platforms - and the related open-source activities in open-source that are required to enable the confidential computing stack on RISC-V platforms. The common/abstract aspects that are cross-architectural will be discussed to enable interoperability across different RISC-V and non-RISC-V platforms. A future roadmap of capabilities will be discussed to encourage participation from the community.

Member Day Closing Keynotes:

• Welcome and remarks (Calista 15 min)
  
• Marketing highlights (Andy or Marketing Chair 15 min)
  
• Technical highlights (Krste or Greg/Philipp as Tech Chairs 20 min)
  
• Community highlights (Megan 10 min)