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October 22-23, 2024
Santa Clara, CA
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strong>ISA and Design Tools [clear filter]
Tuesday, October 22
 

11:30am PDT

Sail RISC-V: Status and Future Challenges
Tuesday October 22, 2024 11:30am - 11:48am PDT
Author: Alasdair Armstrong

In this talk I will present ongoing work as part of the RISC-V golden model working group to develop and maintain the Sail language and  golden reference model for the RISC-V ISA. Sail is an open-source domain-specific language for ISA design and definition, which supports many use-cases, including documentation, use as a reference simulator, relaxed-concurrency semantics, hardware verification, and more.

This talk will describe our vision for the future of the RISC-V golden model. There are many challenges faced by model developers, such as the vast ecosystem of extensions and configurable options supported by RISC-V. We also need to provide a model that is more broadly useful as a source of documentation and learning for the wider RISC-V community.
I will discuss solutions for these challenges, which we intend to address both within the golden model itself, and by co-evolving Sail language itself to better support the unique needs of RISC-V. For example, we are introducing a module system for organising RISC-V extensions, a unified configuration system that supports all the aforementioned Sail use-cases, and enhanced Asciidoctor support for documentation integration.

By presenting this talk, I also hope to be able to engage further with attendees regarding their needs from a golden model.
Tuesday October 22, 2024 11:30am - 11:48am PDT
Theater (Level 2)
  ISA and Design Tools
  • Audience Experience Level Any

11:50am PDT

Load/Store Pair for RV32 (Zilsd & Zclsd) - Christian Herber, NXP
Tuesday October 22, 2024 11:50am - 12:08pm PDT
The Zilsd & Zclsd extensions provide load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings. The extensions are expected to be implemented in all kinds of embedded processors, with optimal performance being reached in core with a data bus of at least 64 bit - a property commonly given in superscalar implementations. The impact on code size of this extension is discussed in detail, leading to recommendations for future compiler improvements.
Speakers
avatar for Christian Herber

Christian Herber

Senior Principal RISC-V Architect, NXP Semiconductors Germany GmbH
Christian Herber is a Senior Principal RISC-V Architect at NXP, working on innovation management and technical roadmaps for RISC-V processors. He led several specification efforts, e.g. the "Load/Store Pair for RV32" RISC-V fast-track extension and the "OpenHW Group Core-V Extension... Read More →
Tuesday October 22, 2024 11:50am - 12:08pm PDT
Theater (Level 2)
  ISA and Design Tools
  • Audience Experience Level Any
  • Session Slides Attached Yes

12:10pm PDT

Applications and Explorations of RISC-V in the Field of Graphics Processing - Siqi Zhao, Alibaba DAMO Academy
Tuesday October 22, 2024 12:10pm - 12:28pm PDT
We introduce the practical applications and innovative explorations of RISC-V processors in the field of graphics processing.Especially the application of RVV in graphics acceleration.
Speakers
avatar for Siqi Zhao

Siqi Zhao

Technology Expert, Alibaba DAMO Academy
Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community. He is currently serving... Read More →
Tuesday October 22, 2024 12:10pm - 12:28pm PDT
Theater (Level 2)

1:55pm PDT

Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis - Sajosh Janarthanam, Tenstorrent Inc.
Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Traditional post silicon HW debug data collection involves the gathering of a snapshot of the design state at the point of failure using scan and an array dump. We propose a hardware mechanism called Debug Signal Trace (DST) that provides the ability to trace a set of design signals over multiple cycles leading to the point of the failure and to store the trace to an on-chip memory like SRAM, or to off-chip System memory. Post processing of the stored debug trace data not only gives debug visibility, but also the ability to build post silicon coverage points. Debug Signal Trace data is timestamped to correlate with instruction trace data. This extends the use-case to SW performance analysis. To ease adoption and usability, the DST control register definition mirrors that of the RISC-V Trace Control Interface which is familiar to the RISC-V debug community. DST supports signal compression to minimize the memory storage footprint. DST leverages the triggers specified in RISC-V Debug Spec while adding user configurable triggers using a select set of design signals.
Speakers
avatar for Sajosh Janarthanam

Sajosh Janarthanam

Principal Engineer, Tenstorrent Inc.
Sajosh has over 20 years of experience in the semiconductor industry, participating in various stages of chip design, from microarchitecture development to post-silicon debug. Currently at Tenstorrent, he is working on RISC-V CPUs and AI SoCs that scale to meet different PPA (Power/Performance/Area... Read More →
Tuesday October 22, 2024 1:55pm - 2:13pm PDT
Theater (Level 2)
  ISA and Design Tools
  • Audience Experience Level Beginner
  • Session Slides Attached Yes

2:15pm PDT

RISC-V CPU Development Using Olympia Performance Model - Knute Lingaard, MIPS
Tuesday October 22, 2024 2:15pm - 2:53pm PDT
The RISC-V Foundation's Olympia Performance Model is a great tool as the basis for designing a high-performance RISC-V CPU design. This session will provide a high-level overview of the Olympia Performance Model and then provide examples of how to use the model for tradeoff analysis on different RISC-V Out-of-Order superscalar designs.
Speakers
avatar for Knute Lingaard

Knute Lingaard

Sr. Principal Engineer, MIPS
Sr. Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. Lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians and co-chair of the RISC-V International Performance Modeling SIG
Tuesday October 22, 2024 2:15pm - 2:53pm PDT
Theater (Level 2)
  ISA and Design Tools

2:55pm PDT

Combined Dynamic and Formal Verification Approach to Processor Verification - Aimee Sutton & Xiaolin Chen, Synopsys
Tuesday October 22, 2024 2:55pm - 3:13pm PDT
With the increased usage of RISC-V processors across the whole range of SoC market segments, quality of the RISC-V processor is an increasingly important issue. Historically, processor IP has been purchased from single-source vendors who own the ISA, and this IP was assumed to be of excellent quality. However, in the RISC-V ecosystem with vendor-supplied IP, open source IP and IP developed in-house, such quality cannot be taken for granted. This creates a verification “disconnect” between SoC developers expecting high-quality IP and processor developers that do not have the verification resources of the single source processor IP vendors. This talk will discuss how dynamic and formal methods can be used together for a more thorough and efficient verification process, helping to bridge the verification disconnect. Examples of using this combined methodology on open-source cores from OpenHW Group, specifically the CV32E40 family, CVW and CVA6, will be presented, including functional coverage results. A key feature of the RISC-V ISA is its extensibility, enabling custom instructions and CSRs to be added. The combined approach will also be shown to work well in this common situation.
Speakers
avatar for Aimee Sutton

Aimee Sutton

Sr. Dir. Product Management, Synopsys
Aimee is currently Sr. Dir. Product Management at Synopsys, responsible for solutions for RISC-V processor verification and system test generation. She has been involved in the design verification space for over 20 years, as both an EDA tool user and EDA tool developer, with Imperas... Read More →
avatar for Xiaolin Chen

Xiaolin Chen

Sr. Director, Applications Engineering, Synopsys
Xiaolin Chen is a Sr. Director of Applications Engineering, formal solutions at Synopsys. She leads a team of applications engineers providing guidance, training, assistance and consulting to semiconductor customers to successfully develop formal technology in verification flow. The... Read More →
Tuesday October 22, 2024 2:55pm - 3:13pm PDT
Theater (Level 2)
  ISA and Design Tools

3:15pm PDT

Enhance the Performance of QEMU RVV Load/Store Implementation - Max Chou, SiFive & Jeremy Bennett, Embecosm
Tuesday October 22, 2024 3:15pm - 3:33pm PDT
QEMU is an emulator that developers can developer and debug their software on it before getting the real RISC-V hardware. We observed that vectorized executables run much slower than non-vectorized ones on QEMU. From benchmarks (e.g. SPEC CPU2k6 h264), we can see that most of the execution time is occupied by RVV load/store instructions. The same observation has been reported in the QEMU community. For example, the glibc memcpy benchmark runs 2x to 60x slower than its scalar equivalent on QEMU. We aim to improve the performance of RVV instructions in QEMU, thereby reducing the execution time required for tasks such as Android bootup. In this talk, we will provide an overview of how we enhanced the performance of QEMU RVV load/store instructions and discuss future work.
Speakers
avatar for Jeremy Bennett

Jeremy Bennett

Chief Executive, Embecosm
Bio: Dr Jeremy Bennett is founder and Chief Executive of Embecosm(http://www.embecosm.com), a consultancy implementing open sourcecompilers, chip simulators and AI/ML for major corporations around the world.He is a author of the standard textbook "Introduction to CompilingTechniques... Read More →
avatar for Max Chou

Max Chou

Staff Software Architecture Engineer, SiFive
Max Chou is a Staff Software - Systems Development Engineer at SiFive. His research interests include binary translation, debugging, optimizations, performance and program analysis tools.
Tuesday October 22, 2024 3:15pm - 3:33pm PDT
Theater (Level 2)
  ISA and Design Tools
 
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